Abstract: Automatically adaptable radix conversion apparatus which provides for radix conversion of an input number by successive serial division using look-up tables contained in a programmable read only memory (PROM). The particular conversion performed is automatically determined in response to input control information provided along with the input number which is used to select the appropriate set of tables in the PROM applicable to the particular conversion desired. The input control information is also used by the apparatus to permit it to automatically adjust to handle variable input number lengths and also to automatically terminate the conversion operation after operations on the last digit of the input number have been completed.

Abstract: Radix conversion apparatus which converts an input number in a first number system into an equivalent output number in a second number system by performing a plurality of successive divisions in accordance with a divide-by-radix iterative equation. A plurality of serial dividers are provided for performing the successive divisions required by the divide-by-radix iterative equation in a manner such that each division is serially performed beginning with the most significant input dividend digit and each output quotient is serially produced beginning with the most significant output quotient digit. The serial dividers are successively arranged so that each can begin its respective division as soon as the first quotient digit is produced by the previous serial divider.

Abstract: An apparatus for converting an input BCD number into its equivalent output binary number in a first mode of operation or an input binary number into its equivalent output BCD number in a second mode of operation. Each input or output number comprises at least one two-digit character. An addressable storage circuit selectively stores the characters of the input number, as well as subsequent interim characters from a combining circuit, in predetermined storage locations. A developing circuit is selectively responsive to each character read out from a storage location and to an associated lower digit of each delayed odd character from a delay circuit for developing an odd addend and an odd multiplier, which are utilized by a first conversion circuit to develop an odd character. The odd character is delayed by the delay circuit to produce the delayed odd character.