Abstract: Disclosed is a Data Valid/Finish circuit element, an integrated circuit using the element, and a method of using the element. The circuit element, which may be incorporated in high speed, digital integrated circuit chips, has an input for receiving input from a data stream, and outputs. One of the outputs is an output true for generating a logical "1" when the input is a logical "1". The other output is an output complementary means for generating a logical "1" when the input is a logical "0". The system logically combines the outputs through an output finish/clock for receiving and combining the outputs of the output true and the output complementary. This generates a logical signal when the input from the data stream is either a logical "0" or a logical "1".

Abstract: A charge transfer device transversal filter is provided including two equivalent charge transfer device shift registers for translating with respect to each other, a first analog signal referred to as an input signal and a second analog signal, referred to as a transfer function signal, with respect to each other. The discrete analog signals are temporarily added on field effect transistor gates. The non-linear characteristics of the field effect transistor performs multiplication. The field effect transistor currents are then summed to complete the filter convolution. The disclosed invention is implemented in either charge-coupled-device technology or bucket-brigade technology.

Abstract: A method and apparatus for duplicating or replicating an original packet of charge carriers such as electrons or holes while leaving the original charge packet unchanged and still available for further processing is described. A charge-coupled device (CCD) circuit is provided using gate displacement charge flow in combination with a bucket brigade circuit. The CCD circuit includes a first +CCD well, a source diffusion and a second CCD well. An original charge packet is introduced into the first CCD well, the gate of which being precharged to a given source potential. The charge packet in the first CCD well reduces the magnitude of the source potential and it is immediately restored by current flow which in turn causes charge carriers to transfer from the source diffusion into the second CCD well until a charge packet is contained in the second CCD well which is a replica of the original charge packet.

Abstract: A transversal filter structure employing charge transfer techniques which are embodied in charge-coupled-devices although bucket brigade devices may also be used. In the structure an input analog signal is time sampled and for each sample a sequence of charge packets Q/2, Q/4, Q/8 . . . Q/2.sup.n is generated. Each sequence of charge packets is entered into a serial charge-coupled-device register and each separate charge packet is then entered into a plurality of n parallel charge-coupled-device registers according to the fractional distribution, i.e. Q1/2, Q2/2, Q3/2 . . . Qk/2 in one register, Q1/4, Q2/4, Q3/4 . . . Qk/4 in another register, up to Q1/2.sup.n, Q2/2.sup.n, Q3/2.sup.n. . . Qk/2.sup.n in a last register. The charge packets in the parallel registers represent the time sampled analog input signal divided by 1, 2, 4, 8, . . . 2.sup.n respectively, and tap weights of +1, -1 and 0 are applied by means of logic control and FET switches.

Abstract: Sense amplifiers employing charge-transfer techniques and cross-coupled devices for use with memory cell arrays or as comparators, polarity sensors and differential amplifiers are described which include a unique preamplifier circuit having cross-coupled actuable devices and which provides a cross-coupled charge-transfer feature. The sense amplifier also includes actuable devices which provide further amplification. The preamplifier circuit includes two precharge actuable devices which have their gate electrode connected to the phase 1 line and which have their source electrode connected through separate capacitors to the phase 2 line. The terminals of the two preamplifier charge-transfer devices which are cross-coupled are also connected at the aforesaid circuit nodes and to the bit/sense lines and to the further amplification devices. The disclosure describes two embodiments of a preamplifier circuit, each of which is shown in combination with a plurality of different further amplification circuits.

Abstract: An input circuit for a charge-transfer-device such as a bucket-brigade or charge-coupled-device incorporating an input terminal connected to an input diode source diffusion of the charge-transfer-device through a capacitor C. The nonlinear depletion capacitance C.sub.d associated with the input circuit is schematically shown connected in parallel with C at a first node. The non-linear capacitance C.sub.d, which is parasitic, is a basic cause of distortion of the input charge packets. The input circuit further includes an active device such as an IGFET connected in parallel with the input terminal to provide a supply of charge carriers. The gate of the active device is connected to a reset signal source.

Abstract: The voltages to be compared are applied to a passive MOS capacitor differencing circuit for producing a voltage difference signal, which then is amplified by a high-gain non-precision FET amplifier, the output of which is passed through a low output impedance FET buffer amplifier to a FET latching circuit. Capacitive coupling is used for enabling the amplifiers to be independently biased and to eliminate D.C. offsets. The operating cycle of the comparator has two periods. During an initial set-up or preconditioning period the amplifiers are self-biased by appropriate switching actions which cause each of the amplifiers to be set at a desired operating point that is maintained when its respective bias switching connection subsequently is opened. The bias switch openings in the respective amplifier and latching stages are timed to occur in a chosen sequence which causes the switching transients to be absorbed.

Abstract: A solid-state charge-coupled photoconductor for image scanning including a p-type substrate having a silicon dioxide layer on the surface thereof with the exception of one or more areas in which an n+ diffusion area is located. A polysilicon gate is located over the silicon dioxide layer and a second silicon dioxide layer is located over the polysilicon layer and the n+ diffusion area except for a portion where a first aluminum contact window is provided which extends through the second silicon dioxide layer to the surface of the n+ diffusion area and where a second aluminum contact window extends through the second polysilicon gate to the surface of the polysilicon gate. The photosensitivity of the device is electronically controlled due to the relatively small n+ layer which is reversed biased with respect to the larger gate area.