Abstract: Techniques are disclosed for processor synchronization within a reconfigurable computing environment for processor array redundancy. Processing elements are configured within a reconfigurable fabric to implement two or more redundant processors, where the two or more redundant processors are enabled for coincident operation. An agent is loaded on each of the two or more redundant processors, where the agent performs a function requiring data validation. The agent is fired on each of the two or more redundant processors to commence coincident operation. The coincident operation can include a lockstep operation. An output data result from each of the two or more redundant processors is compared to enable a data validation result. The data validation result is propagated. The propagating the data validation result can be based on comparing valid output data or can be based on comparing invalid output data.

Abstract: Techniques are disclosed for processor synchronization within a reconfigurable computing environment for processor array redundancy. Processing elements are configured within a reconfigurable fabric to implement two or more redundant processors, where the two or more redundant processors are enabled for coincident operation. An agent is loaded on each of the two or more redundant processors, where the agent performs a function requiring data validation. The agent is fired on each of the two or more redundant processors to commence coincident operation. The coincident operation can include a lockstep operation. An output data result from each of the two or more redundant processors is compared to enable a data validation result. The data validation result is propagated. The propagating the data validation result can be based on comparing valid output data or can be based on comparing invalid output data.

Abstract: A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The coprocessor interface has an instruction transfer signal group for transferring different instruction types from the CPU to the coprocessor, sequentially or in parallel, a busy signal group, for allowing the coprocessor to signal the CPU that it cannot receive a transfer of one or more of the different instruction types, and an instruction order signal group for indicating to the coprocessor a relative execution order for multiple instructions that are transferred in parallel. In addition, the coprocessor interface includes separate data transfer signal groups for data being transferred from the CPU to the coprocessor, and for data being transferred from the coprocessor to the CPU, along with a data order signal group for indicating a relative order of data (if transferred out-of-order).

Abstract: An apparatus and method are provided that enable a central processing unit (CPU) to extend the attributes of virtual memory beyond that which an existing translation lookaside buffer within the CPU is capable of storing while at the same time preserving compatibility with legacy operating system software. The apparatus includes a translation lookaside buffer and extended attributes logic. The translation lookaside buffer (TLB) stores a plurality of TLB entries. Each of the TLB entries has an extended memory attributes index field. The extended attributes logic is coupled to the TLB. The extended attributes logic employs the extended memory attributes index field to access one of a plurality of extended memory attributes registers that is external to the TLB. Contents of the extended memory attributes register prescribe specific extended properties for a corresponding virtual memory page.

Abstract: A microprocessor is implemented using sense amplifiers to replace CMOS logic circuits, in order to provide low voltage, high frequency switching. The input node of the sense amplifier is maintained at a voltage just above or just below their trip-point of one inverter in order to obtain high-speed switching. Bench mark tests have shown that a microprocessor operating at 2.7 volts may obtain a frequency of 20 MHz and while the same microprocessor may operate at 5.5 volts and 40 MHz.

Abstract: A carry skip adder uses independent paths for propagating a skip carry bit and a carry-in bit. Propagation of the carry-in bit is inhibited during a first portion of the clock cycle to prevent spurious carry-in signals from affecting the operation. During this period, other logic functions may be performed, including calculation of the propagation bits and generate bits for each adder block.