Abstract: An integrated circuit structure includes a power supply rail formed in a backside of a semiconductor wafer. The integrated circuit structure also includes a frontside BEOL wire layer connected to the power supply rail through a gate, wherein the gate is of a type to be powered off by a power supply coupled through the gate from the power supply rail to the first frontside BEOL wire layer. A method of forming an integrated circuit structure includes forming a power supply rail in a backside of a semiconductor wafer, forming a gate in the semiconductor wafer, and forming a frontside BEOL wire layer connected to the power supply rail through the gate. Again, the gate is of a type to be powered off by a power supply coupled through the gate from the power supply rail to the first frontside BEOL wire layer.

Abstract: A semiconductor device includes backside power rails located between N channel field effect transistor to N channel field effect transistor spaces, and between at least one P channel field effect transistor to P channel field effect transistor space; and backside local signal lines located between the backside power rails.

Abstract: A semiconductor device includes a porous dielectric layer including a recessed portion, a conductive layer formed in the recessed portion, and a cap layer formed on the porous dielectric layer and on the conductive layer in the recessed portion, an upper surface of the porous dielectric layer being exposed through a gap in the cap layer.

Abstract: A semiconductor structure comprises a first portion of an interconnect line comprising a first conducting line segment and a second conducting line segment separated by an isolating layer, and a second portion of the interconnect line comprising a third conducting line segment vertically stacked over at least a portion of the first conducting line segment and at least a portion of the second conducting line segment.

Abstract: A method is presented forming a fully-aligned via (FAV) and airgaps within a semiconductor device. The method includes forming a plurality of copper (Cu) trenches within an insulating layer, forming a plurality of ILD regions over exposed portions of the insulating layer, selectively removing a first section of the ILD regions in an airgap region, and maintaining a second section of the ILD regions in a non-airgap region. The method further includes forming airgaps in the airgap region and forming a via in the non-airgap region contacting a Cu trench of the plurality of Cu trenches.

Abstract: A microelectronic structure including a plurality of electronic devices. A plurality of frontside contacts, where each of the plurality of frontside contacts is connected to a frontside of one of the plurality electronic devices, respectively. Each of the plurality of frontside contacts is a same first electric potential. A plurality of backside contacts, where the plurality of backside contacts is connected to a backside of one of the plurality of electronic devices, respectively. Each of the plurality of backside contacts is a same second electrical potential, where the first electrical potential is different than the second electrical potential.

Abstract: Embodiments of the present invention are directed to processing methods and resulting structures having hybrid backside dielectrics. In a non-limiting embodiment of the invention, a front end of line structure is formed and a back end of line structure is formed on a first surface of the front end of line structure. A backside power delivery network is formed on a second surface of the front end of line structure opposite the first surface. The backside power delivery network includes a first set of interconnect lines in a first metallization level, a second set of interconnect lines in the first metallization level, and a hybrid backside dielectric structure. The hybrid backside dielectric structure includes a first dielectric material and a second dielectric material. The first set of interconnect lines are embedded in the first dielectric material and the second set of interconnect lines are embedded in the second dielectric material.

Abstract: A dual structure buried rail includes an upper rail and a lower rail. The upper rail may be inset relative to the lower rail. In other words, the lower rail may be wider than the upper rail, and/or the lower rail may have a larger geometrical volume than the upper rail. The upper rail may be located at a boundary of, and/or directly next to, an active device region and the lower rail may extend directly underneath at least a portion of the active device region. The lower rail may extend the entire length of the upper rail. The dual structure buried rail may reduce buried rail resistance which may reduce voltage drop thereacross and provide for improved semiconductor device and/or active device region performance. The dual structure buried rail may provide power potential delivery, provide potential sinking, or the like, to one or more active device region(s).

Abstract: Devices and methods of forming the same include a first conductive line having a top surface at a first height above an underlying layer. A second conductive line, parallel to the first conductive line, has a second height above the underlying layer that is greater than the first height. A first interlayer dielectric layer, between the first conductive line and the second conductive line, has a top surface at a third height above the underlying layer that is greater than the first height and that is less than the second height.

Abstract: A semiconductor interconnect structure comprises a substrate, a plurality of metal lines disposed relative to the substrate and a plurality of first and second caps disposed on the metal lines wherein the first caps comprise a first dielectric material and the second caps comprise a second dielectric material different from the first dielectric material.

Abstract: A liquid-crystalline medium, in particular based on a mixture of polar compounds, having compounds of formulae Y, CY, PY and/or LY, and compounds of formula S1 and/or S2:

Abstract: A liquid-crystalline medium, in particular based on a mixture of polar compounds, having compounds of formulae Y, CY, PY and/or LY, and compounds of formula S1 and/or S2:

Abstract: The present invention relates to wireless telephone networks, and more particularly to the allocation of radio channels to calls in CDMA-based systems when their Radio Access Networks (RAN) are congested. A Base Station (BS) receives a call origination from a mobile device. The BS communicates information about the call and about its radio availability to a Mobile Switching Center (MSC). The MSC determines the priority of the call and how the call should be treated by the BS based on the supplied information. The MSC communicates the treatment information and the priority information back to the BS. When the RAN is congested, high-priority calls are queued. These high-priority calls are served based on allocation specification in which radio channels may be assigned to low-priority calls, which are not queued, while there are still calls in the queue.

Abstract: A test set for testing a device includes a protocol encoder for formatting a plurality of test data in accordance with a channel protocol to create formatted data. A channel encoder encodes the formatted data in accordance with at least one analog channel parameter and at least one analog perturbation parameter to form a link signal. A first link interface produces a channel signal that is coupled to the device. A second link interface generates a received signal that is based on the channel signal.

Abstract: A test set for testing a device includes a protocol encoder for formatting a plurality of test data in accordance with a channel protocol to create formatted data. A channel encoder encodes the formatted data in accordance with at least one analog channel parameter and at least one analog perturbation parameter to form a link signal. A first link interface produces a channel signal that is coupled to the device. A second link interface generates a received signal that is based on the channel signal.

Abstract: Described is an analog delay circuit comprising a gain control circuit to determine a gain of an analog output signal with respect to an analog input signal, and a delay control circuit to determine a group delay of the analog output signal with respect to the analog input signal. The gain control circuit may determine the gain substantially independently of the group delay, and the delay control circuit may determine the group delay substantially independently of the group delay.

Abstract: Disclosed is a transimpendance amplifier comprising a single ended input terminal to receive an input signal from a photodiode and differential output terminals. A circuit coupled between the single ended input terminal and a differential output terminal may vary the gain of the transimpedance amplifier in response to a DC current component of the input signal.

Abstract: Disclosed is a transimpedance amplifier comprising a multi-stage amplifier, a DC current detection circuit to detect a DC current component of an input signal and a DC current removal circuit to substantially remove the DC current component of the input signal.

Abstract: Disclosed is a transimpedance amplifier comprising a multi-stage amplifier, a DC current detection circuit to detect a DC current component of an input signal and a DC current removal circuit to substantially remove the DC current component of the input signal.

Abstract: Disclosed is a transimpedance amplifier comprising a multi-stage amplifier, a DC current detection circuit to detect a DC current component of an input signal and a DC current removal circuit to substantially remove the DC current component of the input signal.