Patents by Inventor Lawrence J. Day

Lawrence J. Day has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210354797
    Abstract: A snorkel assembly includes a mouthpiece and a tube secured thereto. The tube extends between a mouthpiece end and a distal end. A purge valve is disposed adjacent the mouthpiece and the mouthpiece end of the tube. The purge valve allows water and gas to exit the snorkel assembly while preventing water and gas from entering therethrough. The snorkel assembly also includes a check valve secured to the distal end. The check valve allows water and gas to enter the snorkel assembly while preventing water and gas from exiting therethrough.
    Type: Application
    Filed: May 18, 2021
    Publication date: November 18, 2021
    Inventors: Michael L Bottom, Lawrence J Day
  • Publication number: 20190021616
    Abstract: A biometrics device measures a biometric quantity of a body of a user while the user is in motion. The biometric device includes a sensor to measure the biometric quantity of the user and creates a sensed biometric signal. A coupling device couples the sensor to the body of the user. An emitter is electrically connected to the sensor, receives the sensed biometric signal, and emits an output signal to be received by the user such that the user can understand the biometric quantity as the user continues the motion.
    Type: Application
    Filed: January 3, 2018
    Publication date: January 24, 2019
    Inventors: Lawrence J. Day, Michael L. Bottom
  • Patent number: 5594273
    Abstract: Wafer level testing of a wafer (500) is accomplished by dividing the integrated circuits of the wafer into a plurality of segmented bus regions (514, 516, and 518 for example). Each bus region is formed having its own set of test conductors (520-530) wherein each set of test conductors are isolated from all other sets of test conductors on the wafer. Each test conductor has at least one contact pad (531-546) where each contact pad lies within a periphery of the integrated circuits' active areas. By forming pads over ICs and by sub-dividing the bus structure of test conductive lines, more high powered ICs can be tested in a wafer-level manner with fewer problems associated with speed, power, throughput, and routing problems. In addition, all contact pads are formed within the periphery of the ICs but no contact pads are formed over active circuitry so that yield is improved.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: January 14, 1997
    Assignee: Motorola Inc.
    Inventors: Edward C. Dasse, Donald R. Kost, Lawrence J. Day
  • Patent number: 4716302
    Abstract: An integrated circuit has an identifying circuit coupled to an input. The input has ESD protection. The identifying circuit has a fuse which is in one of two possible states to provide the identifying information. A power on reset circuit provides a pulse in response to application of power to the integrated circuit. A current path between a power supply terminal and the input is provided in response to the power on reset pulse when the fuse is in one state. This current path is blocked when the fuse is in the other state. A user is thus provided with identifying information by the presence or absence of a current path at the input at the time when power is applied.
    Type: Grant
    Filed: December 22, 1986
    Date of Patent: December 29, 1987
    Assignee: Motorola, Inc.
    Inventors: Stephen T. Flannagan, Lawrence J. Day, Barry A. Simon
  • Patent number: D706372
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: June 3, 2014
    Inventor: Lawrence J Day