Abstract: A pacemaker having an electrical stimulation source of known type is provided with a sense amplifier having a switched capacitor circuit which allows switching of the amplifier's bandpass frequency characteristic thereby selectively varying the cardiac signal frequencies subject to sensing. The heart's electrical activity is detected in a first predetermined low frequency range after to delivery of a stimuli to detect evoked electrical activity and a second predetermined high frequency range to detect intrinsic electrical activity. The magnitude of stimuli is varied response to the detected presence or absence of evoked electrical activity.

Abstract: A cardiac pacemaker has a sense amplifier responsive to signals representative of cardiac activity for passing signal components lying in a selectively variable pass band and for selectively varying the gain of the passed signal. A pair of signal comparators constituting switched capacitor amplifiers, associated with the sense amplifier, are responsive to the filtered and gain adjusted signal for comparison of its magnitude to predetermined target levels for determination of heart rate and the need for change of rate. Two target levels are provided in each comparator for comparison with the level of the detected signal, by multiplexing the switched capacitors. Another switched capacitor amplifier is used to develop a voltage reference level insensitive to temperature, supply voltage, and circuit components, for deriving the target levels for the comparison.

Abstract: A dual chamber cardiac pacemaker is programmable for either unipolar or bipolar pacing of the atrium or the ventricle, independently of the pacing mode for the other chamber. Transistor switches are utilized for selectively connecting the various anodic electrodes to ground such that one of those electrodes is grounded at all times and isolation is maintained from circuit paths for non-selected modes. Switch control is effected using signals having the highest voltage level of proper polarity in the system, to assure maintenance of the selected switch states despite possible random voltages arising from external influences. Cumulative buildup of charge on coupling capacitors is prevented by selectively and actively discharging them after the respective chamber is paced.

Abstract: An improved voltage level shifter circuit employs pairs of P and N-channel devices which are operated in response to control signals to generate a voltage shifted output signal that corresponds in timing and polarity to an input data signal. The P and N-channel devices interact in latched pairs to maintain logic levels for the output signal. The P-channel and N-channel devices of each pair are disconnected prior to each logic level change for the output signal so that the devices of each pair do not oppose one another in changing the logic level of the output signals.

Abstract: A priority switching circuit for providing a minimum voltage to a voltage sensitive load while charging a second load drawing a high current includes a battery, comparator, capacitor, and a voltage regulator. The output of the comparator causes the battery to be connected to the capacitor whenever the voltage across the capacitor drops below a predetermined minimum and causes the battery to be connected to the high current load when the voltage across the capacitor rises to a predetermined maximum. The circuit provides a varied switching frequency as the internal impedance of the battery increases with age. The voltage regulator provides a constant reference voltage which is used by the comparator to provide the switching control signals.