Patents by Inventor Lawrence Joseph Powell
Lawrence Joseph Powell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8260837Abstract: A system for handling denormal floating point operands when the result must be normalized. A leading zero counter (lzc) on the operand B (opB) is used to limit alignment shifts when opB is denormal but is much greater than the product of operands A and C, i.e. AC. By limiting the additional shift of B during normalization, by the number of leading zeros in opB, no increase is needed in the output bus of the alignment shifter. Furthermore, the additional shift may be done either in the alignment shifter, or postponed to a later stage in the pipeline, where the result is normalized.Type: GrantFiled: September 22, 2008Date of Patent: September 4, 2012Assignee: International Business Machines CorporationInventors: Lawrence Joseph Powell, Jr., Martin Stanley Schmookler, Son Dao Trong
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Patent number: 8024647Abstract: A method of discovering a fault in a circuit is disclosed. The method comprises generating a first result of a selected function by performing the selected function on an operand, wherein the selected function employs a mask. Once the function is performed, an antimask of the mask is created, and the modulo of the antimask is calculated. A modulo function of the first result of the selected function is calculated to obtain a third result. A modulo of the operand is then calculated to obtain a fourth result, and a second function is then performed on the second result and the third result to obtain a fifth result. In response to comparing the fifth result to the fourth result, a signal is propagated to indicate a fault in the circuit.Type: GrantFiled: March 13, 2008Date of Patent: September 20, 2011Assignee: International Business Machines CorporationInventors: Fadi Y. Busaba, Lawrence Joseph Powell, Martin Stanley Schmookler, Michael Thomas Vaden, David Allan Webber
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Patent number: 7657772Abstract: An integrated circuit having a temperature sensitive circuit (TSC) to generate a signal indicative of the substrate temperature near the TSC. The integrated circuit has circuitry configured to receive a TSC signal from at least one TSC and to convert the TSC signal to a signal indicative of the integrated circuit's temperature. The thermal control circuit compares the integrated circuit temperature to a threshold and produces a corrective action signal when the temperature exceeds the threshold. The corrective action signal is provided to corrective action circuitry preferably configured to modify the operation of the IC to reduce the IC temperature in proximity to the corresponding TSC.Type: GrantFiled: February 13, 2003Date of Patent: February 2, 2010Assignee: International Business Machines CorporationInventors: Joachim Gerhard Clabes, Michael Stephen Floyd, Paul David Muench, Lawrence Joseph Powell
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Publication number: 20090077152Abstract: A system for handling denormal floating point operands when the result must be normalized. A leading zero counter (lzc) on the operand B (opB) is used to limit alignment shifts when opB is denormal but is much greater than the product of operands A and C, i.e. AC. By limiting the additional shift of B during normalization, by the number of leading zeros in opB, no increase is needed in the output bus of the alignment shifter. Furthermore, the additional shift may be done either in the alignment shifter, or postponed to a later stage in the pipeline, where the result is normalized.Type: ApplicationFiled: September 22, 2008Publication date: March 19, 2009Applicant: International Business Machines CorporationInventors: Lawrence Joseph Powell, JR., Martin Stanley Schmookler, Son Dao Trong
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Patent number: 7451172Abstract: A method for handling denormal floating point operands when the result must be normalized. A leading zero counter (lzc) on the operand B (opB) is used to limit alignment shifts when opB is denormal but is much greater than the product of operands A and C, i.e. AC. By limiting the additional shift of B during normalization, by the number of leading zeros in opB, no increase is needed in the output bus of the alignment shifter. Furthermore, the additional shift may be done either in the alignment shifter, or postponed to a later stage in the pipeline, where the result is normalized.Type: GrantFiled: February 10, 2005Date of Patent: November 11, 2008Assignee: International Business Machines CorporationInventors: Lawrence Joseph Powell, Jr., Martin Stanley Schmookler, Son Dao Trong
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Publication number: 20080162618Abstract: A method of discovering a fault in a circuit is disclosed. The method comprises generating a first result of a selected function by performing the selected function on an operand, wherein the selected function employs a mask. Once the function is performed, an antimask of the mask is created, and the modulo of the antimask is calculated. A modulo function of the first result of the selected function is calculated to obtain a third result. A modulo of the operand is then calculated to obtain a fourth result, and a second function is then performed on the second result and the third result to obtain a fifth result. In response to comparing the fifth result to the fourth result, a signal is propagated to indicate a fault in the circuit.Type: ApplicationFiled: March 13, 2008Publication date: July 3, 2008Inventors: FADI Y. BUSABA, Lawrence Joseph Powell, Martin Stanley Schmookler, Michael Thomas Vaden, David Allan Webber
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Patent number: 7376890Abstract: A method of discovering a fault in a circuit is disclosed. The method comprises generating a first result of a selected function by performing the selected function on an operand, wherein the selected function employs a mask. Once the function is performed, an antimask of the mask is created, and the modulo of the antimask is calculated. A modulo function of the first result of the selected function is calculated to obtain a third result. A modulo of the operand is then calculated to obtain a fourth result, and a second function is then performed on the second result and the third result to obtain a fifth result. In response to comparing the fifth result to the fourth result, a signal is propagated to indicate a fault in the circuit.Type: GrantFiled: May 27, 2004Date of Patent: May 20, 2008Assignee: International Business Machines CorporationInventors: Fadi Y. Busaba, Lawrence Joseph Powell, Martin Stanley Schmookler, Michael Thomas Vaden, David Allan Webber
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Patent number: 7044633Abstract: The present invention provides a temperature sensitive ring oscillator (TSRO) in an integrated circuit. A temperature measuring device, such as a thermal resistor, is proximate the TSRO, which shares a substantially similar temperature. A memory is employable for storing data that is a function of the output of the TSRO and the temperature measuring device.Type: GrantFiled: January 9, 2003Date of Patent: May 16, 2006Assignee: International Business Machines CorporationInventors: Joachim Gerhard Clabes, Lawrence Joseph Powell, Jr., Daniel Lawrence Stasiak, Michael Fan Wang
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Patent number: 6934658Abstract: Disclosed is an apparatus incorporating hardware based logic and a predetermined default list of software affecting responses to be taken in connection with temperatures sensed by thermal sensors checking the temperature of portions of computer logic. At the time application software is loaded, the software can modify the default response list. The list of responses to be taken and the over temperature conditions at which they are to be activated are stored in hardware directly accessible by hardware based thermal sensor monitoring logic for direct control of the hardware. The control can alter conditions such as clock frequency, stopping use of application software, interrupting OS functionality, removing power from components and so forth.Type: GrantFiled: March 27, 2003Date of Patent: August 23, 2005Assignee: International Business Machines CorporationInventors: Joachim Gerhard Clabes, Lawrence Joseph Powell, Jr., Daniel Lawrence Stasiak, Michael Fan Wang
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Patent number: 6879928Abstract: The present invention provides an integrated circuit VLSI temperature system for the calibration of threshold temperatures. A temperature sensitive ring oscillator (TSRO) generates a TSRO calibration parameter. A memory is employable to store the TSRO calibration parameter. A module is employable to determine a threshold TSRO oscillation frequency from the TSRO calibration parameter. A memory is employable for storing at least one threshold TSRO oscillation frequency.Type: GrantFiled: January 16, 2003Date of Patent: April 12, 2005Assignee: International Business Machines CorporationInventors: Joachim Gerhard Clabes, Lawrence Joseph Powell, Jr., Daniel Lawrence Stasiak, Michael Fan Wang, Balaram Sinharoy, Michael Stephen Floyd
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Publication number: 20040193383Abstract: Disclosed is an apparatus incorporating hardware based logic and a predetermined default list of software affecting responses to be taken in connection with temperatures sensed by thermal sensors checking the temperature of portions of computer logic. At the time application software is loaded, the software can modify the default response list. The list of responses to be taken and the over temperature conditions at which they are to be activated are stored in hardware directly accessible by hardware based thermal sensor monitoring logic for direct control of the hardware. The control can alter conditions such as clock frequency, stopping use of application software, interrupting OS functionality, removing power from components and so forth.Type: ApplicationFiled: March 27, 2003Publication date: September 30, 2004Applicant: International Business Machines CorporationInventors: Joachim Gerhard Clabes, Lawrence Joseph Powell, Daniel Lawrence Stasiak, Michael Fan Wang
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Publication number: 20040159904Abstract: An integrated circuit having a temperature sensitive circuit (TSC) to generate a signal indicative of the substrate temperature near the TSC. The integrated circuit has circuitry configured to receive a TSC signal from at least one TSC and to convert the TSC signal to a signal indicative of the integrated circuit's temperature. The thermal control circuit compares the integrated circuit temperature to a threshold and produces a corrective action signal when the temperature exceeds the threshold. The corrective action signal is provided to corrective action circuitry preferably configured to modify the operation of the IC to reduce the IC temperature in proximity to the corresponding TSC.Type: ApplicationFiled: February 13, 2003Publication date: August 19, 2004Applicant: International Business Machines CorporationInventors: Joachim Gerhard Clabes, Michael Stephen Floyd, Paul David Muench, Lawrence Joseph Powell
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Publication number: 20040143410Abstract: The present invention provides an integrated circuit VLSI temperature system for the calibration of threshold temperatures. A temperature sensitive ring oscillator (TSRO) generates a TSRO calibration parameter. A memory is employable to store the TSRO calibration parameter. A module is employable to determine a threshold TSRO oscillation frequency from the TSRO calibration parameter. A memory is employable for storing at least one threshold TSRO oscillation frequency.Type: ApplicationFiled: January 16, 2003Publication date: July 22, 2004Applicant: International Business Machines CorporationInventors: Joachim Gerhard Clabes, Lawrence Joseph Powell, Daniel Lawrence Stasiak, Michael Fan Wang
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Publication number: 20040135643Abstract: The present invention provides a temperature sensitive ring oscillator (TSRO) in an integrated circuit. A temperature measuring device, such as a thermal resistor, is proximate the TSRO, which shares a substantially similar temperature. A memory is employable for storing data that is a function of the output of the TSRO and the temperature measuring device.Type: ApplicationFiled: January 9, 2003Publication date: July 15, 2004Applicant: International Business Machines CorporationInventors: Joachim Gerhard Clabes, Lawrence Joseph Powell, Daniel Lawrence Stasiak, Michael Fan Wang
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Patent number: 6725307Abstract: A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. The node controller receives commands from a master device, communicates with a master device as another master device or as a slave device, and queues commands received from a master device. Due to pin limitations that may be caused by large buses, e.g. buses that support a high number of data pins, the node controller may be implemented such that the functionality for its address paths and data paths are implemented in physically separate components, chips, or circuitry, such as a node data controller or a node address controller.Type: GrantFiled: September 23, 1999Date of Patent: April 20, 2004Assignee: International Business Machines CorporationInventors: Manuel Joseph Alvarez, II, Joel Roger Davidson, Sanjay Raghunath Deshpande, Peter Dau Geiger, Lawrence Joseph Powell, Praveen S. Reddy
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Patent number: 6684232Abstract: During execution of floating point convert to integer instructions, the necessity for incrementing the instruction result during rounding is predicted early and utilized to predict the result sign, to produce an implied bit which will achieve the correct result with round determination logic for standard floating point instructions, and to set up rounding mode, guard and sticky bits allowing the standard round determination logic to be utilized during rounding of the floating point convert to integer instruction result. The minimum logic required to control incrementing of a standard floating point instruction result during rounding may therefore be reused for floating point convert to integer instructions without increasing the critical path for rounding and without significantly adding to the complexity of the floating point execution unit.Type: GrantFiled: October 26, 2000Date of Patent: January 27, 2004Assignee: International Business Machines CorporationInventors: Glen Howard Handlogten, James Edward Phillips, Lawrence Joseph Powell, Martin Stanley Schmookler
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Patent number: 5896516Abstract: A protocol and apparatus for crossbar switches where the cycle time is too short to allow the updating of the input/output buffer controls by the arbitration logic in one cycle. The crossbar switch has separate data paths and commands paths. Two types of commands are sent over the crossbar switches. The first type is an address (A) only command which consist of a single packet needing one clock cycle. The second type of command is an Address with Data command (AD), consisting of two through nine packets, and requiring a maximum of nine clock cycles. A command becomes a request through two different paths through the crossbar switch. The first path is via an input bypass path which allows an input command buffer to be bypassed and a request written directly to a multiplexer. The second path is through the input command buffer which is written but not selected until processing is completed for the previous command.Type: GrantFiled: June 30, 1997Date of Patent: April 20, 1999Assignee: International Business Machines CorporationInventors: Lawrence Joseph Powell, Jr., Krishnamurthy Venkatramani