Abstract: A technique for permitting data transfers between a high speed bus and a low speed bus which operate independently and asynchronously wherein when the low speed bus requires access to the high speed bus, the busy status of the latter bus is determined and transfers are made to the high speed bus at high speed when such bus is not busy. When the high speed bus requires access to the low speed bus, if the low speed bus is busy the requesting master on the high speed bus is temporarily placed in a pending status and is removed from its tenure on the high speed bus, so that the high speed bus is free to handle other requests. When the low speed bus is free, the highest priority pending requestor is provided access to the low speed bus on a priority basis over all then current requestors.

Abstract: A method for performing address and data transfers among a plurality of different units of a data processing system having a system bus which includes an address bus and a data bus. The system uses arbitration phase, address transfer phase, and data transfer phase operations which require the use of unique handshake signals at each phase so as to permit address and data transfers to occur on a suitable priority basis with respect to different ones of such units in a pipelined manner using non-multiplexed, asynchronous operations.

Abstract: An improved memory system for use in a data processing system which memory system has two memory banks and corresponding error correction circuitry associated with each. Data words of a block thereof are stored in the memory banks in an interleaved fashion wherein alternating words are stored in one bank and intervening alternating words are stored in the other bank. During a write operation the memory is controlled so that the first data word of a block stored in a memory bank uses a late write technique and all subsequent data words thereof use an early write technique. During a read operation, pairs of data words are read and checked for errors simultaneously and are then supplied in a pipelined manner.

Abstract: A data processing system having a host processor and an attached processor is disclosed. Each processor is capable of executing user programs under a different operating system and each processor is capable of accessing system memory but the host processor controls and performs all input and output operations for both processors. System memory is shared by the processors, therefore, only one processor is active on the bus system at any given time. Apparatus is disclosed for holding the host processor and starting the attached processor upon a command from the host and apparatus is disclosed for holding the attached processor and starting the host in the event of interrupt conditions, attempted access by the attached processor to protected areas of memory, or execution of an "out" instruction by the attached processor. Memory mapping apparatus which is under host control, but provides mapping for both the host and attached processors is shown.