Abstract: An architecture for a high speed memory circuit having a relatively large number of internal data lines is shown to include global read and write data lines, and power and ground lines extending laterally across the array. The laterally extending lines are preferably within the third layer of metal. Preferably, the only other metal interconnect over the memory arrays is in the first metal layer, which is used to strap the word lines. Sense amp bands extend longitudinally along the borders of each memory cell bank. Local read and write data lines and read and write column select lines extend through the sense amp bands. Power and ground lines also extend through each sense amp band. Preferably, the architecture includes read path circuitry including a local read circuit that selectively isolates the global read data lines from the local read data lines.

Abstract: A reduced capacitance architecture for integrated circuits and particularly for memory integrated circuits is disclosed. The integrated circuit has a plurality of levels including first and second levels. A first signal conductor extends within the first level. A second signal conductor also extends within the first level and is positioned adjacent to and in close proximity with the first signal conductor. The second level is positioned adjacent to the first level and includes a third signal conductor extending within it. The third signal conductor is positioned laterally between the first and second conductors to eliminate vertical parallel plate capacitance.