Abstract: A technique for conserving digital memory space is disclosed. This technique includes sequentially transmitting a first address and a second address on a first bus coupled to a FIFO memory. The first address is stored in the memory and compared to the second address to determine a first value corresponding to a difference between the first and second addresses. This first value is written in the memory to represent the second address and has a bit size smaller than the second address. A method to decode the first value to regenerate the second address is also disclosed. These techniques may be further enhanced by only storing an address in a sequential access memory when it differs from the most recently stored address in the memory.

Abstract: A processing system and method is disclosed to access non-contiguous memory locations within a memory block. An address is generated that has a first group of bits and a second group of bits. The first group is decoded to select one of a number of memory blocks. The second group has n bits configured to select any one of (2.sup.n -(n+1)) unique combinations of the locations within the selected block. This second group provides a different pattern corresponding to each different combination of the locations within the selected block. An application of this addressing scheme for video graphics processing is also disclosed.