Abstract: A method of protecting an underlying diffusion barrier layer in a dual damascene trench and via etch process with a coating of negative photoresist. The dual damascene process starts with via hole etching in an intermetal dielectric (IMD) layer. Next, the thin film barrier layer is deposited and patterned to fill the bottom of the vias. The key process step is a coating of negative photoresist which is exposed and developed to partially fill the via openings. This thick layer of negative photoresist in the vias protects the thin diffusion barrier layer from subsequent dual damascene etch processing.

Abstract: A method of protecting an underlying diffusion barrier layer in a dual damascene trench and via etch process with a coating of negative photoresist. The dual damascene process starts with via hole etching in an intermetal dielectric (IMD) layer. Next, the thin film barrier layer is deposited and patterned to fill the bottom of the vias. The key process step is a coating of negative photoresist which is exposed and developed to partially fill the via openings. This thick layer of negative photoresist in the vias protects the thin diffusion barrier layer from subsequent dual damascene etch processing.

Abstract: A method to form dual damascene structures is described. A substrate layer is provided. An anti-diffusion layer is deposited. A first dielectric layer is deposited. An etch stopping layer is deposited. A second dielectric layer is deposited. The second dielectric layer, the etch stopping layer, and the first dielectric layer are patterned to form the vias. A liner layer is deposited overlying the second dielectric layer and internal surfaces of the lower trenches. The liner layer and the second dielectric layer are patterned to form the upper trenches. The liner layer and the anti-diffusion layer are etched through to complete the formation of the dual damascene structure, and the integrated circuit device is completed.