Abstract: The present invention, generally speaking, provides an improved power amplifier that minimizes impedance changes as the power amplifier changes from one operational state to another. In an exemplary embodiment, the present power amplifier is based on the well-known cascode amplifier. In a cascode amplifier, a first transistor operates in the common-source (common emitter) configuration to convert the input signal voltage (or current) into an amplified current, and a second transistor operates in the common-gate (common-base) configuration to convert the output current from the first transistor into an output voltage.

Abstract: Electrical supply current, sufficient to power a wireless access point, is transmitted concurrently with a network data signal across a transmission line. A power and data coupler couples the network data signal and the power signal, received through a data input and a power input respectively, and transmits the coupled signal, to a distance of three meters or more, over the transmission line to a power and data decoupler. The power and data decoupler separates the power signal from the network data signal and supplies those signals to a power output port and a data output port, respectively, for use by a wireless access node. The power signal may be modulated at a low frequency relative to the frequency of the data signal, and the network data signal has a data transmission rate of one megabit/second or higher.

Abstract: Component mounting pads for multi-layer printed circuit boards encompass a smaller area than conventional pads, reducing parasitic capacitance between the pads and a ground plane layer. A number of such pads are arranged to accommodate standard surface-mount component sizes and packages. Further capacitance reductions are achieved by implementing mesh areas or apertures in the board's ground plane opposite the reduced-capacitance pads.

Abstract: A broad band tunable microstrip antenna is realized. A substrate layer with a high dielectric constant is placed between a radiating element and a ground plane layer. The electrically conductive radiating element is fabricated on the substrate layer such that a main patch surrounded by a number of individual tuning patches connected to the main patch and to each other are provided. During the tuning process, the effective length and effective width can be selectively adjusted by disconnecting individual tuning patches. In addition to broadening the bandwidth of the microstrip antenna, the optimal feed point can be selected. In other embodiments, the individual tuning patches are initially disconnected from each other and the main patch. During the tuning process, the individual tuning patches are selectively connected or soldered to the main patch. Furthermore, tuning can also be accomplished by connecting or disconnecting individual tuning patches to obtain the desired dimensions of the radiating element.

Abstract: Electrical supply current, sufficient to power a wireless access point, is transmitted concurrently with a network data signal across a transmission line. A power and data coupler couples the network data signal and the power signal, received through a data input and a power input respectively, and transmits the coupled signal, to a distance of three meters or more, over the transmission line to a power and data decoupler. The power and data decoupler separates the power signal from the network data signal and supplies those signals to a power output port and a data output port, respectively, for use by a wireless access node. The power signal may be modulated at a low frequency relative to the frequency of the data signal, and the network data signal has a data transmission rate of one megabit/second or higher.

Abstract: An antenna system for use in wireless communication systems that is based on a pair of monopole antennas, which are electrically isolated from each other and arranged generally orthogonally. A feed circuit is coupled to the first and second monopole antennas, which connects them to a host system. Also, a ground plane conductor extends generally between the feeds for the first and second monopole antennas to improve isolation. The monopole antennas are formed on a printed circuit board, formed on first and second dielectric layers. A ground plane conductive film is disposed between the dielectric layers. The first monopole antenna is formed on an outside surface of the first dielectric layer, and the second monopole antenna is formed on the outside surface of the second dielectric layer. The second monopole antenna is arranged generally orthogonally to the first monopole antenna.

Abstract: A micro-power, micro-size RF detector is suitable for implementation on an integrated circuit. The detector is used for detecting the presence of high frequency AC signals on a transmission line which has a transmission line impedance. An input for connection to the transmission line through a high impedance relative to the transmission line is provided. A current mode detector is coupled to the input. The current mode detector translates AC signals on the input to a bias signal having a DC component determined by power of the AC signal on the transmission line. A current mode amplifier is coupled to the current mode detector, and amplifies the bias signal to produce a detector current. A binary output driver is coupled to the current mode amplifier, which generates a binary signal having one binary level if the detector current exceeds a high signal threshold, and another binary level if the detector current falls below a low signal threshold.

Abstract: The number of input latching comparators in a flash analog-to-digital converter is significantly reduced by merging the input latching function into exclusive OR gates used in the converter's decoding section. A latching exclusive OR gate used for this purpose employs resonant tunneling diodes as the latching devices, with hysteresis and impedance elements connected to ensure that the gate latches in a logic state that corresponds to the input analog signal. The latching logic gates operate in a current mode, enabling updated logic states to be latched in response to a periodic clock signal.

Abstract: An antenna system for a communication device which receives and/or transmits packets of data having a characteristic reception interval comprises first and second antennas which are spatially diverse. A feed circuit is coupled to the first and second antennas to connect the first and second antennas to the communication device. The feed circuit includes a switching circuit and an oscillating switch driver which periodically select the first antenna and the second antenna, with a period which is normally substantially greater than the characteristic reception interval for the communication system. For example, if the period of the switching circuit is about one hundred milliseconds, and the data packet length is only 1.22 milliseconds as in the case of Ethernet, then many packets can be transmitted during each antenna configuration state. If both states are such that neither antenna is in a multipath null then no packets are dropped.

Abstract: A current reference combines proportional to absolute temperature and complementary to absolute temperature current sources to produce a current reference that is relatively immune to power supply variations and features a temperature coefficient which may be adjusted to yield a positive, negative or zero tempco. In its preferred embodiment, the new current reference may be advantageously employed within an analog to digital converter (ADC) to yield equal quantization values in spite of variations in the ADC's supply voltage and temperature. Additionally, the tempco may be adjusted to permit the ADC's quantization valued to "track" variations in circuitry which produce the analog signals converted by the ADC.

Abstract: An apparatus for detecting errors in a wireless communication channel comprises a receiver which receives a data stream from the wireless communication channel, a signal strength indication circuit coupled with the receiver which indicates signal strength for a received data stream, and processing resources coupled to the signal strength indication circuit which monitors the received data signal strength to detect anomalies in the strength of the received data stream, typical of erroneous data. Also, the system includes a signal phase monitoring circuit coupled with the receiver. This circuit indicates phase of the received data stream. Processing resources coupled with the signal phase monitoring circuit, monitor the received data stream phase to detect anomalies in phase of the received data stream typical of erroneous data. In addition, the data stream will include data packets having error detection codes imbedded within the data packets.

Abstract: The number of input latching comparators in a flash analog-to-digital converter is significantly reduced by merging the input latching function into exclusive OR gates used in the converter's decoding section. A latching exclusive OR gate used for this purpose employs resonant tunneling diodes as the latching devices, with hysteresis and impedance elements connected to ensure that the gate latches in a logic state that corresponds to the input analog signal. The latching logic gates operate in a current mode, enabling updated logic states to be latched in response to a periodic clock signal.

Abstract: A receiver for NRZ data does not require a separate transmission media for the clock. Rather, a clock recovery circuit is included in the receiver capable of recovering the clock based on transitions detected in the NRZ data alone. The clock recovery circuit comprises an edge detection circuit which receives the data stream and generates edge detection signals indicating transitions in the data stream. Reference clock generation circuity generates a plurality of reference clock signals shifted in phase with respect to one another. Phase quantizing circuitry is responsive to the edge detection signals and the plurality of reference clock signals. The phase quantizing circuitry generates a quantization signal indicating one of the plurality of reference clock signals having a particular phase relationship to the edge detection signals.

Abstract: A collision detection method and apparatus which is suitable for use in a wireless CSMA/CD network, or other wireless networks where collision detection is provided. The apparatus includes a detector which detects intermodulation or other mixing products of colliding data transmissions at a station in the network, and a signal processor which indicates collisions between the data transmissions based upon characteristics of the intermodulation products. The system is capable of detecting collisions, both between transmissions from the station on which the device is located and transmissions from other sources, and between two transmissions being received from other sources. The station includes a transmitter having an input for a data packet. Resources coupled to the input add a header to the data packet, the header having characteristics monitored by the collision detector circuitry including a pseudo-random bit sequence.

Abstract: A time of arrival detector for an analog pulse signal digitizes the pulse, digitally delays the digitized signal in one path and converts the delayed signal back to a delayed analog version of the input signal. In a second path an undelayed analog version of the input signal is provided. A scaling offset is established to scale the delayed signal larger than the undelayed signal, and the delayed and undelayed signals are then compared to establish a time of arrival for the input pulse. A delta modulator is preferably used to provide the digitized signal, and also to provide the undelayed analog version of the input signal as the smoothed output of an integrator within the delta modulator. The undelayed modulator output is preferably attenuated by -3 dB, with the pulse's time of arrival obtained from the time at which the delayed analog signal rises above the undelayed but attenuated signal.

Abstract: A high speed, low distortion amplifier is implemented with all npn transistors by providing a correction circuit that responds to changes in the amplifier's input voltage by substantially reducing current variations in the input stage. This is accomplished with the use of a current source resistor for the second branch of the differential input stage, together with a correction circuit that diverts a portion of the resistor's current away from the input stage's second branch. The diverted current varies negatively with the input voltage, and thus compensates for input stage current variations that would result in the absence of the correction circuit. A differential amplifier with one branch biased in response to the input voltage and the other branch held at a constant bias is preferably used to establish the correction current. The invention is applicable to open loop amplifiers, fed forward closed loop amplifiers and bootstrapped closed loop amplifiers.

Abstract: A latching comparator circuit employs latching devices having a region of negative impedance separating regions of higher and lower positive impedance, such as resonant tunnel diodes, to significantly increase operating speed. The latching devices are biased so that one of them is triggered into its higher voltage region of positive impedance when a latching operation is desired, and the other is held in its lower voltage region of positive impedance. Hysteresis elements drive the triggered device to a lower voltage level within its higher voltage region, while a cross-coupling circuit between the latching devices holds the non-triggered device in its lower voltage region below its trigger level, thus assuring circuit stability.