Abstract: A harmonic detector including a pattern detector circuit responsive to a clock signal and a data signal configured to detect a target bit pattern from said data signal, and a time-out circuit responsive to said pattern detector circuit configured to detect the absence of said target bit pattern during a predetermined time-out parameter for indicating when said clock signal exceeds said data signal by a factor of two or more.

Abstract: A rotational frequency detector system including a rotational frequency detector responsive to a data signal and a clock signal. The rotational frequency detector is configured to compare the frequency of the clock signal to the frequency of the data signal to define frequency up and frequency down signals that adjust the frequency of the clock signal to be equal to the frequency of the data signal. A step control system is responsive to the rotational frequency detector and a step clock signal and is configured to define predetermined pulse widths for the frequency up and frequency down signals.

Abstract: An improved coarse frequency detector includes a first storage device responsive to a data signal and a sub-multiple of a clock signal for detecting a first transition in the data signal during a predetermined state of the sub-multiple of the clock signal and generating an intermediate signal, and a second storage device responsive to the data signal and the intermediate signal for detecting a second transition in the data signal having the same polarity as the first transition during the predetermined state of the sub-multiple of the clock signal and generating an up-pulse.

Abstract: An adjustable offset voltage circuit is disclosed for applying an offset voltage to a differential voltage in a digital data receiver system. The circuit includes a pair of emitter follower units, and a pair of current generating units. The first emitter follower unit provides a first offset voltage, and the second emitter follower unit provides a second offset voltage. The first current generating unit provides a biasing current to the first emitter follower unit, and the second current generating unit provides a biasing current to the second emitter follower unit. The circuit also includes a pair of differential signal input ports, each of which is coupled to one of the first and second emitter follower units, and an offset adjustment unit for permitting offset adjustment of a differential output signal with respect to a differential input signal at the input ports.

Abstract: A frequency locked loop for providing an output signal having an output frequency within a predetermined range of a non-integer multiple of a reference frequency. The frequency locked loop includes a voltage element, such as a voltage controlled oscillator, which produces the output signal at the output frequency. The frequency locked loop further includes a fractional divider which is operably coupled to the voltage controlled oscillator. Further, the frequency locked loop includes a frequency detector, such as a rotational frequency detector, which is operably coupled to the fractional divider. The frequency detector receives the reference signal, such as a fixed clock signal, and the output of the fractional divider signal and outputs a frequency detector signal. In one embodiment, the rotational frequency detector responds to cycle slips of 2&pgr; radians between the reference frequency and the output signal of the fractional divider.

Abstract: A tunable oscillator for producing an output signal includes an input for receiving a first voltage that is a function of the output signal, a controllable oscillator, and a voltage element that produces a second voltage and has a first leak current. The controllable oscillator produces the output signal based upon the first and second voltages, and the first leak current causes the second voltage to fluctuate. The tunable oscillator also includes a current generator operatively coupled with the input. The current generator produces a generator current that is a function of the first voltage, where the first voltage is responsive to fluctuations in the second voltage. The generator current compensates for the fluctuations in the second voltage.

Abstract: Low jitter ring oscillators are disclosed. The oscillators obtain their low jitter through the use of gates (100) and interpolators (160) having time delays of superior stability. The stability is obtained with decoupling networks (140) and delay replica generators (222) that isolate power supply noise from critical circuit parameters.

Abstract: A monolithic interface circuit for use with a linear variable differential transformer (LVDT) position transducer. The interface circuit includes a drive circuit for providing an excitation signal of selectable frequency and amplitude to the LVDT primary winding. The interface circuit further includes a decoder responsive to signals induced in the LVDT secondary windings for computing the position p of the LVDT core as a solution to the equation p=K(A-B)/(A+B), where A and B represent the signals induced in the primary winding and K is a constant scale factor. The decoder includes circuitry for rectifying and filtering the secondary signals, a charge balance loop responsive to the detected signals for providing a binary signal having a duty cycle representative of B/(A+B), and an output circuit responsive to the binary signal for providing the position output. The decoder provides excellent scale factor stability and linearity and is relatively insensitive to variations in primary drive amplitude.

Abstract: A monolithic interface circuit for use with a linear variable differential transformer (LVDT) position transducer. The interface circuit includes a drive circuit for providing an excitation signal of selectable frequency and amplitude to the LVDT primary winding. The interface circuit further includes a decoder responsive to signals induced in the LVDT secondary windings for computing the position p of the LVDT core as a solution to the equation p=K(A-B)/(A+B), where A and B represent the signals induced in the primary winding and K is a constant scale factor. The decoder includes circuitry for rectifying and filtering the secondary signals, a charge balance loop responsive to the detected signals for providing a binary signal having a duty cycle representative of b/(A+B), and an output circuit responsive to the binary signal for providing the position output. The decoder provides excellent scale factor stability and linearity and is relatively insensitive to variations in primary drive amplitude.

Abstract: A phase-detector circuit for a phase-locked loop clock recovery system detects the phase difference between an information signal and a clock signal and produces a phase error signal representative of the phase difference. The phase detector includes, in one embodiment, five latches, serially interconnected, with the first latch receiving the information signal and each subsequent latch receiving the data output of the previous latch. The latches are enabled, in an alternating pattern, by the high-level and low-level portions of the clock signal. A first exclusive-OR (XOR) gate receives a delayed information signal and the data output of the second latch. A second XOR gate receives the data output of the second latch and the data output of the third latch. A third XOR gate receives the data output of the third latch and the data output of the fourth latch. A fourth XOR gate receives the data output of the fourth latch and the data output of the fifth latch.

Abstract: A monlithic interface circuit for use with a linear variable differential transformer (LVDT) position transducer. The interface circuit includes a drive circuit for providing an excitation signal of selectable frequency and amplitude to the LVDT primary winding. The interface circuit further includes a decoder responsive to signals induced in the LVDT secondary windings for computing the position p of the LVDT core as a solution to the equation p=K(A-B)/(A+B), where A and B represent the signals induced in the primary winding and K is a constant scale factor. The decoder includes circuitry for rectifying and filtering the secondary signals, a charge balance loop responsive to the detected signals for providing a binary signal having a duty cycle representative of B/(A+B), and an output circuit responsive to the binary signal for providing the position output. The decoder provides excellent scale factor stability and linearity and is relatively insensitive to variations in primary drive amplitude.

Abstract: A voltage-to-frequency converter comprising a triwave generator responsive to an input signal to produce an output triangular signal the frequency of which corresponds to the magnitude of the input signal, and a voltage-slope-to-periodic-function (VSTPF) generator which receives the output of the triwave generator and produces a pulsed output signal having a frequency which is a multiple of that of the triwave generator.