Abstract: A microcode control memory having a first memory for receiving initial instructions is shown in combination with at least one additional memory for executing multistep control functions in a computer system. The first memory receives all initial control instructions from an instruction stack and produces the appropriate control output. Simultaneously as part of the initial instruction, a memory select network receives a control bit so that an output select network connected to the output of all memories passes the output from the first memory to the output register. Single step instructions are processed continuously this way. Multistep instructions are performed by using a portion of the output from the first memory to serve as the address selection in one of the other memories. When a multistep instruction is completed, the output select network again selects the output from the first memory for gating to the output register.

Abstract: In a microcode control memory for a computer central processing unit, a network is provided for generating a modified microcode address in a sequence of instructions where the modified address is determined by a function of the results of preselected events.

Abstract: A microcode addressing system is shown which has two modes of operation for different memory search functions. The first mode, the Slow mode in which the memory operates at a standard read rate, is the mode in which the computer central processing unit performs predetermined sequential tasks in a normal fashion. The second mode of operation is the Fast mode of operation in which the memory responds to unpredetermined, dynamically changing events in the computer system at a faster than standard cycle time in order to search for and identify a particular word in central memory.