Abstract: A customizable interconnect circuit wherein a universal substrate of minimum layers is completely customized by programmable conductive links placed only on the top layer of the substrate. The customizable circuit having high density of orthogonally placed X- and Y-conductors capable of interconnecting closely spaced large-scale integrated circuits or discrete electrical components. By utilizing a plurality of interconnect cells regularly spaced throughout a universal, fixed substrate, interconnect routing from overlying electrical components or integrated circuits can be more directly routed to target areas.

Abstract: A customizable circuit using a programmable interconnect and a compatible tape design for tape automated bonding of chips to the circuitry. The programmable interconnect comprises layers of wires, with one layer of wires forming overlap regions with the adjacent layer of wires. The wires can be selectively linked later to form the desired interconnect. The selective linkage represents the customization of an otherwise undedicated interconnect. The TAB chip bonding design uses a carrier tape to bond the integrated circuit chips to the programmable interconnect. Also disclosed is a method for forming the interconnect.

Abstract: An electrical beam switch for interconnection between a plurality of inputs and outputs and includes a two-dimensional array of electrically charged particle emitters and an array of detectors facing the emitter array for receiving charged particles from various of the emitters. X and y electrical deflectors are positioned adjacent each of the emitters for directing the charged particles from each of the emitters to a selected one or more of the detectors. A screen lens may be positioned adjacent the array of detectors for focusing the directed beams on to the selected detector.

Abstract: A high density electrical interconnect having a plurality of metallic conductors supported from metallic pillars which are electrically isolated from the ground plane by openings. The interconnect can be fabricated using a temporary support dielectric, which may be removed after completion to provide an air dielectric or be replaced with a more suitable permanent dielectric. The removal of the temporary support allows the conductors to be coated with protective layers or with a layer of a higher conductivity.

Abstract: A thin film capacitor having a top, middle and bottom plate forming two capacitors in series in which the middle plate is a plurality of isolated plates thereby forming a structure of a plurality of two capacitors in series which are all connected in parallel. The capacitor may be integrated into an electronic substrate. The capacitor may be formed by depositing films of the metal conductors and dielectrics and may be formed as an integral part of a semiconductor chip or interconnect substrate.

Abstract: A customizable circuit using a programmable interconnect and a compatible tape design for tape automated bonding of chips to the circuitry. The programmable interconnect comprises layers of wires, with one layer of wires forming overlap regions with the adjacent layer of wires. The wires can be selectively linked later to form the desired interconnect. The selective linkage represents the customization of an otherwise undedicated interconnect. The TAB chip bonding design uses a carrier tape to bond the integrated circuit chips to the programmable interconnect. Also disclosed is a method for forming the interconnect.

Abstract: Superconductive integrated logic gate circuits of the magnetically controlled type incorporating Josephson tunnel junctions utilize a superconductive layer that forms a base electrode for Josephson junction devices on the integrated circuit, a ground plane, and magnetic control lines. A layer of super-conductive material superposed on a barrier layer provides inductive loops connected to junction counterelectrodes and coupled to the magnetic control lines. By patterning the control lines in the same plane as the ground plane-base electrode layer, two layers, an insulating layer and a super-conductive layer, can be eliminated from the prior art structure of a 1:2:1 magnetically controlled logic gate interferometer. A preferred embodiment utilizing an all refractory superconductor-barrier-superconductor trilayer patterned by local anodization is also described. Processes for manufacturing the embodiments of the invention are disclosed.

Abstract: A superconductive junction device for fabricating Josephson integrated circuits is useful for replacing deposited thin-film resistors. Derived by "poisoning" a superconductive electrode of the Josephson junction, the device displays controllable resistive properties at normal superconducting transition temperatures at substantial savings in the space occupied. Methods of fabricating the device using the selective niobium anodization process and conventional lead alloy processes are disclosed. When both upper and lower superconductive electrodes are poisoned, the device has linear properties whose resistance is identical to the normal resistance of unpoisoned junctions.

Abstract: A superconductive tunnel junction device comprises first and second superconductive electrodes with a barrier disposed therebetween where the first superconductive electrode and the barrier are formed without interruption in the same vacuum system pump down and with the first superconductive electrode subjected to sputter etching in an argon plasma before the deposition of the barrier for improving the characteristics of the device.

Abstract: Superconductive tunnel junctions are manufactured with precise junction areas by defining a narrow-line junction of precise width utilizing a narrow-line mask of precise width and thereafter applying a second narrow-line mask of precise width at an angle to the narrow-line junction to define a junction area with dimensions precisely controlled by the widths of the narrow-line masks. "Edge lithography" is preferably utilized to provide the narrow-line masks.

Abstract: Josephson junction integrated circuits of the current injection type and magnetically controlled type utilize a superconductive layer that forms both Josephson junction electrode for the Josephson junction devices on the integrated circuit as well as a ground plane for the integrated circuit. Large area Josephson junctions are utilized for effecting contact to lower superconductive layers and islands are formed in superconductive layers to provide isolation between the groundplane function and the Josephson junction electrode function as well as to effect crossovers. A superconductor-barrier-superconductor trilayer patterned by local anodization is also utilized with additional layers formed thereover. Methods of manufacturing the embodiments of the invention are disclosed.

Abstract: Josephson junction integrated circuits of the current injection type and magnetically controlled type utilize a superconductive layer that forms both Josephson junction electrode for the Josephson junction devices on the integrated circuit as well as a ground plane for the integrated circuit. Large area Josephson junctions are utilized for effecting contact to lower superconductive layers and islands are formed in superconductive layers to provide isolation between the groundplane function and the Josephson junction electrode function as well as to effect crossovers. A superconductor-barrier-superconductor trilayer patterned by local anodization is also utilized with additional layers formed thereover. Methods of manufacturing the embodiments of the invention are disclosed.