Abstract: In a pipeline processor, simultaneous decoding of multiple specifiers in a variable-length instruction causes a peculiar problem of an intra-instruction read conflict that occurs whenever an instruction includes an autoincrement or an autodecrement specifier which references either directly or indirectly a register specified by a previously occurring specifier for the current instruction. To avoid stalls during the preprocessing of instructions by the instruction unit, register pointers rather than register data are usually passed to the excellent unit because register data is not always available at the time of instruction decoding. If an intra-instruction read conflict exists, however, the operand value specified by the conflicting register specifier is the initial value of the register being incremented or decremented, and this initial value will have been changed by the time that the execution unit executes the instruction.

Abstract: A self time register (STREG) 44 is constructed on a single custom ECL integrated circuit and has provisions for generating its own internal clock signal. The STREG 44 includes a set of latches 80a-80q for temporarily storing the data delivered thereto concurrent with the system clock pulse. Thereafter, the internally generated clock pulse (W.sub.PULS) controls the write operation of the temporary latches into the STREG 44. The STREG has data storage registers including bit storage cells which receive the data in response to the internally generated clock pulse. To selectively output the data, the bit storage cells have emitter-coupled output selectors, and the output selectors for common bits share a common current sink and a common pull-up resistor at which a single-bit output signal is provided from a selected register. Preferably, each bit storage cell has a first output selector for a first data output port, and a second output selector for a second data output port.