Abstract: In one aspect, a method comprises providing at least two identical front-end-of-line (FEOL) portions of an integrated circuit (IC) in a single wafer, with at least some of each FEOL portion comprising a plurality of circuit elements; building a design back-end-of-line (BEOL) portion of the IC on at least one of the FEOL portions to form a product chip, with the design BEOL portion configuring design-type interconnections of the same plurality of circuit elements for a first instantiation; building a test-only BEOL structure on at least one of the FEOL portions to form a sacrificial test device, with the test-only BEOL structure configuring test-type interconections of the same plurality of circuit elements for a second instantiation; and testing the sacrificial test device for at least one of functionality or reliability.

Abstract: This disclosure relates to a memory device that includes at least one magnetic track on a substrate, wherein the at least one magnetic track comprises one or more magnetic domains. Contacts can be disposed on the at least one magnetic track according to a predetermined arrangement to form a plurality of bitcells on the at least one magnetic track, wherein each one of the plurality of bitcells is configured to store at least one magnetic domain. The device can include a timing circuit connected to the contacts, with the timing circuit being configured to apply to the contacts multiple phases of electric currents according to a predetermined timing sequence to cause the at least one magnetic domain to shift from the each one of the plurality of bitcells to an adjacent one of the plurality of bitcells on the at least one magnetic track.

Abstract: Methods of calculating optimal power flows (OPFs) in power transmission and distribution networks using equivalent-circuit formulations that allow the solutions to converge to corresponding global minima. In some aspects, network (circuit) elements are modeled using split circuits composed of real and imaginary parts. A variety of nonlinear OPF problem formulations are disclosed, including direct-solution formulations and iterative-solution formulations based on converting real and reactive power constraints to equivalent conductance/susceptance constraint. Also disclosed are a variety of techniques for solving the disclosed OPF problems, including new admittance-stepping homotopy techniques, among others. Software embodying disclosed methods is also described, as are example implementation scenarios.

Abstract: An approach to modeling the nonlinear steady-state behavior of an electrical power grid in terms of equivalent circuits with currents and voltages as state variables is provided. Current and voltage conservation equations are formulated with circuit-theoretic algorithms that offer demonstrably superior robustness relative to traditional approaches. Generalized bus and line models are accommodated by the equivalent circuit-based approach, allowing for simulation of physical models not compatible with traditional methods. Unbalanced three-phase systems are handled without loss of generality. The provided methods allow for robust, efficient power flow simulation for contingency analysis, power system planning, power system design, power system control, component configurations and operating conditions, real-time scheduling, and optimization, among other applications.

Abstract: A method includes receiving a data bit value at a buffer in a bitcell based on a first state of a write bitline connected to the buffer, and transferring the data bit value from the buffer to a first magnetic switching cell in the bitcell for a later read operation at least by holding the write bitline to a reference value different from the first state, and asserting first and second predetermined voltage levels on respective first and second write wordlines connected to the buffer.

Abstract: In one aspect, a method comprises providing at least two identical front-end-of-line (FEOL) portions of an integrated circuit (IC) in a single wafer, with at least some of each FEOL portion comprising a plurality of circuit elements; building a design back-end-of-line (BEOL) portion of the IC on at least one of the FEOL portions to form a product chip, with the design BEOL portion configuring design-type interconnections of the same plurality of circuit elements for a first instantiation; building a test-only BEOL structure on at least one of the FEOL portions to form a sacrificial test device, with the test-only BEOL structure configuring test-type interconections of the same plurality of circuit elements for a second instantiation; and testing the sacrificial test device for at least one of functionality or reliability.

Abstract: In one aspect, a magnetic data storage device comprises a template layer, an underlayer, and a magnetic recording layer. The template layer includes a patterned array of protruding features. The underlayer is formed on the patterned array of protruding features of the template layer. The underlayer includes an array pattern of protruding features that aligns with the patterned array of protruding features of the template layer. The magnetic recording layer is formed on the underlayer. The magnetic recording layer includes columnar grains of magnetic material separated by grain boundaries of non-magnetic material, with each columnar grain being on a protruding feature of the array pattern of the underlayer, and the grain boundaries being in trenches between the protruding features of the array pattern of the underlayer.

Abstract: A method includes receiving a data bit value at a buffer in a bitcell based on a first state of a write bitline connected to the buffer, and transferring the data bit value from the buffer to a first magnetic switching cell in the bitcell for a later read operation at least by holding the write bitline to a reference value different from the first state, and asserting first and second predetermined voltage levels on respective first and second write wordlines connected to the buffer.

Abstract: In one aspect, a nonvolatile magnetic logic device comprises an electrically insulating layer, a write path, and a read path. The write path comprises a plurality of write path terminals and a magnetic layer having a uniform magnetization direction that is indicative of a direction of magnetization of the magnetic layer in a steady state. A logic state is written to the nonvolatile magnetic logic device by passing a current through the plurality of write path terminals. The read path comprises a plurality of read path terminals for evaluation of the logic state. The electrically insulating layer promotes electrical isolation between the read path and the write path and magnetic coupling of the read path to the write path.

Abstract: In one aspect, a nonvolatile magnetic logic device comprises an electrically insulating layer, a write path, and a read path. The write path comprises a plurality of write path terminals and a magnetic layer having a uniform magnetization direction that is indicative of a direction of magnetization of the magnetic layer in a steady state. A logic state is written to the nonvolatile magnetic logic device by passing a current through the plurality of write path terminals. The read path comprises a plurality of read path terminals for evaluation of the logic state. The electrically insulating layer promotes electrical isolation between the read path and the write path and magnetic coupling of the read path to the write path.

Abstract: Configurable circuits using phase change switches are described. The switches use phase change or phase transition material to create configurable connections between devices and/or interconnecting layers of an integrated circuit in order to change the behavior of the circuit after manufacturing. In at least some embodiments, the phase of the material can be a crystalline phase or an amorphous phase. A phase change can be caused by heating the material, such as with an ohmic heater fabricated on the IC. As one example, germanium-antimony-tellurium (GeSbTe) can be used for the phase change material. The switches can be used to create configurable circuits such as low noise amplifiers and mixers, which can in turn be used to create configurable receivers or other analog circuits.

Abstract: The large-scale process and environmental variations for today's nano-scale ICs are requiring statistical approaches for timing analysis and optimization (1). Significant research has been recently focused on developing new statistical timing analysis algorithms (2), but often without consideration for how one should interpret the statistical timing results for optimization. The invention provides a sensitivity-based metric (2) to assess the criticality of each path and/or arc in the statistical timing graph (4). The statistical sensitivities for both paths and arcs are defined. It is shown that path sensitivity is equivalent to the probability that a path is critical, and arc sensitivity is equivalent to the probability that an arc sits on the critical path. An efficient algorithm with incremental analysis capability (2) is described for fast sensitivity computation that has a linear runtime complexity in circuit size.

Abstract: The invention provides a method and process for designing an integrated circuit based on using the results from both 1) a specific set of silicon test structure characterizations and 2) the decomposition of logic into combinations of simple logic primitives, from which a set of logic bricks are derived that can be assembled for a manufacturable-by-construction design. This implementation of logic is compatible with the lithography settings that are used for implementation of the memory blocks and other components on the integrated circuit, particularly by implementing geometrically consistent component features. The invention provides the ability to recompile a design comprised of logic and memory blocks onto a new geometry fabric to implement a set of technology-specific design changes, without requiring a complete redesign of the entire integrated circuit.

Abstract: Optimization design method for configurable analog circuits and devices resulting from same. An implementation fabric for a given application domain can be accurately pre-characterized in terms of devices and parasitics. Customization structures are designed and characterized to be applied to the fabric to customize a device for a particular application. In some embodiments, characterization is accomplished by formulating a configurable design problem as an optimization with recourse problem, for example, a geometric programming with recourse (GPR) problem. Devices can be produced for multiple applications from the application domain using the same optimized fabric to provide predictable performance.

Abstract: The large-scale process and environmental variations for today's nano-scale ICs are requiring statistical approaches for timing analysis and optimization (1). Significant research has been recently focused on developing new statistical timing analysis algorithms (2), but often without consideration for how one should interpret the statistical timing results for optimization. The invention provides a sensitivity-based metric (2) to assess the criticality of each path and/or arc in the statistical timing graph (4). The statistical sensitivities for both paths and arcs are defined. It is shown that path sensitivity is equivalent to the probability that a path is critical, and arc sensitivity is equivalent to the probability that an arc sits on the critical path. An efficient algorithm with incremental analysis capability (2) is described for fast sensitivity computation that has a linear runtime complexity in circuit size.

Abstract: Configurable circuits using phase change switches are described. The switches use phase change or phase transition material to create configurable connections between devices and/or interconnecting layers of an integrated circuit in order to change the behavior of the circuit after manufacturing. In at least some embodiments, the phase of the material can be a crystalline phase or an amorphous phase. A phase change can be caused by heating the material, such as with an ohmic heater fabricated on the IC. As one example, germanium-antimony-tellurium (GeSbTe) can be used for the phase change material. The switches can be used to create configurable circuits such as low noise amplifiers and mixers, which can in turn be used to create configurable receivers or other analog circuits.

Abstract: A system to test integrated circuits on a wafer may include a transceiver formed on the wafer. The system may also include an antenna system couplable to the transceiver. The transceiver may be formed in one of a scribe line on the wafer, a chip on the wafer or on an otherwise unusable portion of the wafer. The antenna system maybe formed in at least one of the same scribe line as the transceiver or in at least one other scribe line formed in the wafer. Alternatively, the antenna system may include an antenna external to the wafer.

Abstract: Active resistors for reduction of transient power grid noise. An active resistance added in parallel to the operating circuit blocks of a semiconductor device. This resistance increases the damping ratio of the power grid, which in turn decreases the number and the magnitude of oscillations and/or noise resulting from step disturbances of the power supply current. The active resistance can implemented by a transistor connected to a bias voltage. Alternatively, the active resistance can be implemented by a drive transistor with a gain stage, or two active resistors where one responds to overshoots in the current flow and the second active resistor responds to droops in the current flow.

Abstract: The invention provides a method and process for designing an integrated circuit based on using the results from both 1) a specific set of silicon test structure characterizations and 2) the decomposition of logic into combinations of simple logic primitives, from which a set of logic bricks are derived that can be assembled for a manufacturable-by-construction design. This implementation of logic is compatible with the lithography settings that are used for implementation of the memory blocks and other components on the integrated circuit, particularly by implementing geometrically consistent component features. The invention provides the ability to recompile a design comprised of logic and memory blocks onto a new geometry fabric to implement a set of technology-specific design changes, without requiring a complete redesign of the entire integrated circuit.

Abstract: Analog and radio frequency system-level simulation using frequency relaxation. Embodiments of the invention use a frequency relaxation approach for analog/RF system-level simulation that accommodates both large system size and complex signal space. The simulator can determine an output response for a system by partitioning the system into blocks and simulating the propagation of an input signal through the blocks. The input signal can take various forms, including a multi-tone sinusoidal signal, a continuous spectra signal, and/or a stochastic signal. Frequency relaxation is applied to produce individual responses. The output response can be computed based on obtaining convergence of the individual responses. The input to embodiments of the simulator can be a circuit netlist, or a block-level macromodel.