Abstract: A semiconductor device (20) is fabricated by doping a dielectric layer (29) located over the surface of a semiconductor substrate (21). The dielectric layer (29) contains nitrogen and is doped with silicon ions by using an ion implantation process (15) such that a peak concentration (32) of the silicon ions remains in the dielectric layer (29) during the ion implantation process (15). Doping the dielectric layer (29) reduces charge trapping in the dielectric layer (29) and reduces power slump in the semiconductor device (20) during high frequency operation.

Abstract: A method for forming a metal pattern on a substrate (11) includes forming a dielectric stack (14) on a major surface (12) of the substrate (11) and forming a mask (22) on the dielectric stack (14). The dielectric stack (14) includes an aluminum nitride layer (16) serving as an etch stop layer between two dielectric layers (15, 17). An opening is formed in the dielectric stack (14) via successive etching. The etching of the dielectric layer (15) between the aluminum nitride layer (16) and the substrate (11) undercuts the aluminum nitride layer (16). A metal layer (30) is deposited on the major surface through the opening via sputtering. The metal layer (30) on the major surface is distinctively separated from a metal layer (34) on the edge of the opening. The mask (22) is dissolved in a solvent, thereby lifting-off a metal layer (34) deposited on the mask (22).

Abstract: A method for etching aluminum containing layers. A layer (13) of aluminum nitride is formed on a semiconductor substrate (11). The layer (13) of aluminum nitride is etched using a dilute ammonium hydroxide solution that is diluted with water such that the ammonium hydroxide solution has one part of ammonium hydroxide to at least fifteen parts of water. The dilute ammonium hydroxide solution is showered onto the semiconductor substrate and forms an aluminum hydroxide layer. The aluminum hydroxide layer is dissolved by excess water in the dilute aluminum hydroxide solution and rinsed from the semiconductor substrate (11).

Abstract: A method of manufacturing a gate structure (19) for a semiconductor device (10) utilizes a dielectric layer (17) containing aluminum to protect the surface of a substrate (11) from residues resulting from deposition and etching of the gate structure (19). The gate structure (19) forms a refractory contact to the substrate (11), and the source and drain regions (26) are self-aligned to the gate structure (19). Semiconductor devices manufactured using methods in accordance with the present invention are observed to have a higher breakdown voltage and a higher transconductance, among other improved electrical performance characteristics.

Abstract: A field effect transistor (10) has an active layer (16) formed in a substrate (12). A gate (20) is disposed on an elevated platform (18) formed from the active layer (16). The elevated platform (18) raises the bottom surface (21) of the gate (20) relative to the top surface (34, 36) of the active region (13) on either side of the gate (20). A fabrication method for the transistor (10) forms the elevated platform (18) by etching the active region surface (44) on both sides of the gate (20) so that the bottom surface (21) of the gate (20) is elevated relative to the top surface (34) of the surrounding active region (13). The gate (20) itself and/or a patterned photoresist layer (116) may be used as a mask for performing this etch.

Abstract: A field effect transistor (10) has an active layer (16) formed in a substrate (12). A gate (20) is disposed on an elevated platform (18) formed from the active layer (16). The elevated platform (18) raises the bottom surface (21) of the gate (20) relative to the top surface (34, 36) of the active region (13) on either side of the gate (20). A fabrication method for the transistor (10) forms the elevated platform (18) by etching the active region surface (44) on both sides of the gate (20) so that the bottom surface (21) of the gate (20) is elevated relative to the top surface (34) of the surrounding active region (13). The gate (20) itself and/or a patterned photoresist layer (116) may be used as a mask for performing this etch.

Abstract: A semiconductor device having a short gate length is fabricated. The short gate length is obtained by utilizing the fact that an unannealed silicon nitride can be isotropically etched while not etching an annealed silicon nitride layer. The method comprises forming a first silicon nitride 13 on a semiconductor material 10, annealing layer 13, forming an insulating layer 15, a second silicon nitride layer 17 and a masking layer 19, undercutting a portion of layers 17 and 15, removing the masking layer, annealing the second silicon nitride 17, implanting to form channel region 20 having portions 21 and 22, undercutting a portion of the insulating layer 15, removing the second silicon nitride 17 and the first silicon nitride 13 not covered by layer 15, forming gate 23 having effective gate length 30 and source/drain 25/26.