Abstract: An N-channel, double level poly, MOS read only memory or ROM array is electrically programmable by floating gates, and electrically erased power voltages applied to the source, drain, control gate and substrate. The floating gate discharges through the insulator between the floating gate and the control gate, i.e., between first and second level polysilicon. An enhancement mode transistor in series with the floating gate device in each cell provides an improved voltage window for deprogramming by allowing the transistor created by the floating gate to go into the depletion mode. The threshold of this series enhancement transistor is lowered by an implant step in the process which is self-aligning.

Abstract: An N-channel, double level poly, MOS read only memory or ROM array is electrically programmable by floating gates which are interposed between the gate oxide and control gates formed by row address lines. The cells may be electrically erased by applying selected voltages to the source, drain, control gate and substrate; the floating gate discharges through the insulator between the floating gate and the control gate, i.e., between first and second level polysilicon.