Patents by Inventor Lawrence Selvaraj SUSAI
Lawrence Selvaraj SUSAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11935678Abstract: An inductive device may be provided, including a first winding layer, a second winding layer arranged over the first winding layer and connected to the first winding layer to form a plurality of turns around a first axis, and a magnetic core arranged vertically between the first winding layer and the second winding layer. The magnetic core may include a portion entirely over the first winding layer and entirely under the second winding layer, where this portion may include a magnetic segment and a non-magnetic segment arranged laterally adjacent to each other along the first axis.Type: GrantFiled: December 10, 2020Date of Patent: March 19, 2024Assignee: GLOBALFOUNDARIES SINGAPORE Pte. Ltd.Inventors: Zishan Ali Syed Mohammed, Lulu Peng, Chor Shu Cheng, Yong Chau Ng, Lawrence Selvaraj Susai
-
Patent number: 11901445Abstract: A transistor may include a buffer layer, source and drain contacts on the buffer layer, a barrier layer on the buffer layer, a conductive member on the barrier layer, a dielectric stack, and a gate metal. The barrier layer may be between the source and drain contacts. The conductive member may include a p-doped III-V compound. The dielectric stack may be on the barrier layer and on the conductive member. The dielectric stack may include a first dielectric layer and a second dielectric layer on the first dielectric layer. First and second trenches may extend through the dielectric stack to the conductive member and to the first dielectric layer, respectively. The gate metal may be on the dielectric stack, and may contact the conductive member through the first trench and may contact the first dielectric layer through the second trench.Type: GrantFiled: November 13, 2020Date of Patent: February 13, 2024Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Jiacheng Lei, James Jerry Joseph, Lawrence Selvaraj Susai, Shyue Seng Tan
-
Patent number: 11888051Abstract: Structures for a high-electron-mobility transistor and methods of forming a structure for a high-electron-mobility transistor. The high-electron-mobility transistor has a first semiconductor layer, a second semiconductor layer adjoining the first semiconductor layer along an interface, a gate electrode, and a source/drain region. An insulator region is provided in the first semiconductor layer and the second semiconductor layer. The insulator region extends through the interface at a location laterally between the gate electrode and the source/drain region.Type: GrantFiled: May 8, 2020Date of Patent: January 30, 2024Assignee: GlobalFoundries Singapore Pte. Ltd.Inventors: Jiacheng Lei, Lawrence Selvaraj Susai, Joseph James Jerry
-
Publication number: 20240021716Abstract: Structures including compound semiconductor-based devices and silicon-based devices integrated on a semiconductor substrate and methods of forming such structures. The structure comprises a layer stack on a substrate, a conductive contact extending in a vertical direction fully through the layer stack to the substrate, and a device structure including a source ohmic contact and a drain ohmic contact. The layer stack including a plurality of semiconductor layers each comprising a compound semiconductor material, the conductive contact is arranged in the layer stack to separate a first portion of the layer stack from a second portion of the layer stack, and the source ohmic contact and the drain ohmic contact have a contacting relationship with at least one of the plurality of semiconductor layers of the first portion of the layer stack.Type: ApplicationFiled: July 14, 2022Publication date: January 18, 2024Inventors: Lawrence Selvaraj Susai, Handoko Linewih, Francois Hebert, Hendro Mario, Siow Lee Chwa
-
Patent number: 11538751Abstract: A semiconductor device is provided. The semiconductor device comprises an inductor in a far back end of line layer and a capacitor adjacent to and electrically coupled with the inductor. The capacitor comprises a first electrode layer arranged over sidewalls and a bottom surface of a via in a first insulating layer A dielectric layer is provided over the first electrode layer. A second electrode layer is provided over the dielectric layer and a metal fill layer is provided over the second electrode layer. The metal fill layer has a top surface at least level with a top surface of the first insulating layer.Type: GrantFiled: September 3, 2020Date of Patent: December 27, 2022Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Lulu Peng, Nur Aziz Yosokumoro, Zishan Ali Syed Mohammed, Lawrence Selvaraj Susai, Chor Shu Cheng, Yong Chau Ng
-
Patent number: 11476043Abstract: An inductive device may be provided, including a substrate and an inductive structure arranged over the substrate. The inductive structure may include a bottom metal winding layer; a top metal winding layer arranged further away from the substrate than the bottom metal winding layer; a magnetic core layer arranged between the bottom metal winding layer and the top metal winding layer; a connector arranged to electrically connect the bottom metal winding layer and the top metal winding layer; and a top metal ring element arranged around the top metal winding layer, spaced apart from the top metal winding layer. The inductive device may further include a guard ring element arranged under the top metal ring element and around the magnetic core layer, spaced apart from the magnetic core layer; wherein the guard ring element may include a magnetic material.Type: GrantFiled: December 30, 2019Date of Patent: October 18, 2022Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Zishan Ali Syed Mohammed, Lulu Peng, Lawrence Selvaraj Susai, Chor Shu Cheng
-
Patent number: 11444168Abstract: A transistor device may be provided, including a substrate; a buffer layer arranged over the substrate; a source terminal, a drain terminal, and a gate terminal arranged over the buffer layer; a barrier layer arranged over the buffer layer; and a passivation layer arranged over the barrier layer. The gate terminal may be arranged laterally between the source terminal and the drain terminal, the barrier layer may include a recess laterally between the gate terminal and the drain terminal, a part of the gate terminal may be arranged over the passivation layer and the passivation layer may extend into the recess of the barrier layer.Type: GrantFiled: November 2, 2020Date of Patent: September 13, 2022Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Jiacheng Lei, James Jerry Joseph, Khee Yong Lim, Lulu Peng, Lawrence Selvaraj Susai
-
Patent number: 11380677Abstract: According to various embodiments, a transistor device may include a semiconductor structure having a trench formed therein. The semiconductor structure may include a buffer layer and a barrier layer arranged over the buffer layer. The trench may extend at least to the buffer layer. The transistor device may include a source terminal, a drain terminal, and a gate terminal arranged between the source terminal and the drain terminal. The gate terminal may extend into the trench. The transistor device may include an electrode component. The electrode component may include an electrode. The electrode component may extend into the trench where the electrode component is separated from the gate terminal. The electrode component may contact a side wall of the trench.Type: GrantFiled: April 28, 2020Date of Patent: July 5, 2022Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Jiacheng Lei, Lawrence Selvaraj Susai
-
Publication number: 20220189673Abstract: An inductive device may be provided, including a first winding layer, a second winding layer arranged over the first winding layer and connected to the first winding layer to form a plurality of turns around a first axis, and a magnetic core arranged vertically between the first winding layer and the second winding layer. The magnetic core may include a portion entirely over the first winding layer and entirely under the second winding layer, where this portion may include a magnetic segment and a non-magnetic segment arranged laterally adjacent to each other along the first axis.Type: ApplicationFiled: December 10, 2020Publication date: June 16, 2022Inventors: Zishan Ali SYED MOHAMMED, Lulu PENG, Chor Shu CHENG, Yong Chau NG, Lawrence Selvaraj SUSAI
-
Publication number: 20220157977Abstract: A transistor may include a buffer layer, source and drain contacts on the buffer layer, a barrier layer on the buffer layer, a conductive member on the barrier layer, a dielectric stack, and a gate metal. The barrier layer may be between the source and drain contacts. The conductive member may include a p-doped III-V compound. The dielectric stack may be on the barrier layer and on the conductive member. The dielectric stack may include a first dielectric layer and a second dielectric layer on the first dielectric layer. First and second trenches may extend through the dielectric stack to the conductive member and to the first dielectric layer, respectively. The gate metal may be on the dielectric stack, and may contact the conductive member through the first trench and may contact the first dielectric layer through the second trench.Type: ApplicationFiled: November 13, 2020Publication date: May 19, 2022Inventors: Jiacheng LEI, James JERRY JOSEPH, Lawrence Selvaraj SUSAI, Shyue Seng TAN
-
Publication number: 20220140096Abstract: A transistor device may be provided, including a substrate; a buffer layer arranged over the substrate; a source terminal, a drain terminal, and a gate terminal arranged over the buffer layer; a barrier layer arranged over the buffer layer; and a passivation layer arranged over the barrier layer. The gate terminal may be arranged laterally between the source terminal and the drain terminal, the barrier layer may include a recess laterally between the gate terminal and the drain terminal, a part of the gate terminal may be arranged over the passivation layer and the passivation layer may extend into the recess of the barrier layer.Type: ApplicationFiled: November 2, 2020Publication date: May 5, 2022Inventors: Jiacheng LEI, James JERRY JOSEPH, Khee Yong LIM, Lulu PENG, Lawrence Selvaraj SUSAI
-
Publication number: 20220068809Abstract: A semiconductor device is provided. The semiconductor device comprises an inductor in a far back end of line layer and a capacitor adjacent to and electrically coupled with the inductor. The capacitor comprises a first electrode layer arranged over sidewalls and a bottom surface of a via in a first insulating layer A dielectric layer is provided over the first electrode layer. A second electrode layer is provided over the dielectric layer and a metal fill layer is provided over the second electrode layer. The metal fill layer has a top surface at least level with a top surface of the first insulating layer.Type: ApplicationFiled: September 3, 2020Publication date: March 3, 2022Inventors: LULU PENG, NUR AZIZ YOSOKUMORO, ZISHAN ALI SYED MOHAMMED, LAWRENCE SELVARAJ SUSAI, CHOR SHU CHENG, YONG CHAU NG
-
Publication number: 20210351286Abstract: Structures for a high-electron-mobility transistor and methods of forming a structure for a high-electron-mobility transistor. The high-electron-mobility transistor has a first semiconductor layer, a second semiconductor layer adjoining the first semiconductor layer along an interface, a gate electrode, and a source/drain region. An insulator region is provided in the first semiconductor layer and the second semiconductor layer. The insulator region extends through the interface at a location laterally between the gate electrode and the source/drain region.Type: ApplicationFiled: May 8, 2020Publication date: November 11, 2021Inventors: Jiacheng Lei, Lawrence Selvaraj Susai, Joseph James Jerry
-
Publication number: 20210335778Abstract: According to various embodiments, a transistor device may include a semiconductor structure having a trench formed therein. The semiconductor structure may include a buffer layer and a barrier layer arranged over the buffer layer. The trench may extend at least to the buffer layer. The transistor device may include a source terminal, a drain terminal, and a gate terminal arranged between the source terminal and the drain terminal. The gate terminal may extend into the trench. The transistor device may include an electrode component. The electrode component may include an electrode. The electrode component may extend into the trench where the electrode component is separated from the gate terminal. The electrode component may contact a side wall of the trench.Type: ApplicationFiled: April 28, 2020Publication date: October 28, 2021Inventors: Jiacheng LEI, Lawrence Selvaraj SUSAI
-
Publication number: 20210202165Abstract: An inductive device may be provided, including a substrate and an inductive structure arranged over the substrate. The inductive structure may include a bottom metal winding layer; a top metal winding layer arranged further away from the substrate than the bottom metal winding layer; a magnetic core layer arranged between the bottom metal winding layer and the top metal winding layer; a connector arranged to electrically connect the bottom metal winding layer and the top metal winding layer; and a top metal ring element arranged around the top metal winding layer, spaced apart from the top metal winding layer. The inductive device may further include a guard ring element arranged under the top metal ring element and around the magnetic core layer, spaced apart from the magnetic core layer; wherein the guard ring element may include a magnetic material.Type: ApplicationFiled: December 30, 2019Publication date: July 1, 2021Inventors: Zishan Ali SYED MOHAMMED, Lulu PENG, Lawrence Selvaraj SUSAI, Chor Shu CHENG
-
Publication number: 20210111243Abstract: A semiconductor device may include: a substrate; a protective region provided over the substrate; and a core structure enclosed by the protective region. The core structure may include a core material etchable by a chemical solution. The protective region may include a protective material resistant to etching by the chemical solution. The core structure may have a first side and a second side opposite to the first side, the first side being closer to the substrate than the second side. The core structure may be narrowest at the first side of the core structure.Type: ApplicationFiled: October 15, 2019Publication date: April 15, 2021Inventors: Lawrence Selvaraj SUSAI, Chor Shu CHENG, Yong Chau NG, Lulu PENG, Zishan Ali SYED MOHAMMED, Nuraziz YOSOKUMORO
-
Patent number: 10825888Abstract: Integrated circuits (ICs) and method for forming IC devices are presented. In one embodiment, a method of forming a device with an integrated magnetic component using 3-dimensional (3-D) printing is disclosed. The method includes providing a substrate with a base dielectric layer, the base dielectric layer serves as a base for the integrated magnetic component. A first metal layer is formed on the substrate by spray coating metal powder over the substrate and performing selective laser melting on the metal powder. A magnetic core is formed on the substrate by spray coating magnet powder over the substrate and performing selective laser sintering on the magnet powder. A second metal layer is formed on the substrate by spray coating metal powder over the substrate and performing selective laser melting on the metal powder. A patterned dielectric layer separates the first and second metal layers and the magnetic core.Type: GrantFiled: June 27, 2019Date of Patent: November 3, 2020Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Lulu Peng, Donald Ray Disney, Lawrence Selvaraj Susai, Rajesh Sankaranarayanan Nair
-
Publication number: 20190319085Abstract: Integrated circuits (ICs) and method for forming IC devices are presented. In one embodiment, a method of forming a device with an integrated magnetic component using 3-dimensional (3-D) printing is disclosed. The method includes providing a substrate with a base dielectric layer, the base dielectric layer serves as a base for the integrated magnetic component. A first metal layer is formed on the substrate by spray coating metal powder over the substrate and performing selective laser melting on the metal powder. A magnetic core is formed on the substrate by spray coating magnet powder over the substrate and performing selective laser sintering on the magnet powder. A second metal layer is formed on the substrate by spray coating metal powder over the substrate and performing selective laser melting on the metal powder. A patterned dielectric layer separates the first and second metal layers and the magnetic core.Type: ApplicationFiled: June 27, 2019Publication date: October 17, 2019Inventors: Lulu PENG, Donald Ray DISNEY, Lawrence Selvaraj SUSAI, Rajesh Sankaranarayanan NAIR
-
Patent number: 10446639Abstract: Integrated circuits (ICs) and method for forming IC devices are presented. In one embodiment, a method of forming a device with an integrated magnetic component using 3-dimensional (3-D) printing is disclosed. The method includes providing a substrate with a base dielectric layer, the base dielectric layer serves as a base for the integrated magnetic component. A first metal layer is formed on the substrate by spray coating metal powder over the substrate and performing selective laser melting on the metal powder. A magnetic core is formed on the substrate by spray coating magnet powder over the substrate and performing selective laser sintering on the magnet powder. A second metal layer is formed on the substrate by spray coating metal powder over the substrate and performing selective laser melting on the metal powder. A patterned dielectric layer separates the first and second metal layers and the magnetic core.Type: GrantFiled: March 29, 2017Date of Patent: October 15, 2019Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Lulu Peng, Donald Ray Disney, Lawrence Selvaraj Susai, Rajesh Sankaranarayanan Nair
-
Publication number: 20180286940Abstract: Integrated circuits (ICs) and method for forming IC devices are presented. In one embodiment, a method of forming a device with an integrated magnetic component using 3-dimensional (3-D) printing is disclosed. The method includes providing a substrate with a base dielectric layer, the base dielectric layer serves as a base for the integrated magnetic component. A first metal layer is formed on the substrate by spray coating metal powder over the substrate and performing selective laser melting on the metal powder. A magnetic core is formed on the substrate by spray coating magnet powder over the substrate and performing selective laser sintering on the magnet powder. A second metal layer is formed on the substrate by spray coating metal powder over the substrate and performing selective laser melting on the metal powder. A patterned dielectric layer separates the first and second metal layers and the magnetic core.Type: ApplicationFiled: March 29, 2017Publication date: October 4, 2018Inventors: Lulu PENG, Donald Ray DISNEY, Lawrence Selvaraj SUSAI, Rajesh Sankaranarayanan NAIR