Abstract: A switching regulator that has first, second, third and fourth terminals, a first power transistor disposed between the first terminal and a first node, a second power transistor disposed between the first node and a second node, a filter including a capacitor and an inductor, and a controller. The first power transistor is partitioned into a plurality of individually-addressable first transistor segments. The second node couples the second and fourth terminals. The second power transistor is partitioned into a plurality of individually-addressable second transistor segments. The inductor is disposed between the first node and the third terminal, and the capacitor is disposed between the third and fourth terminals.

Abstract: A switching regulator that has first, second, third and fourth terminals, a first power transistor disposed between the first terminal and a first node, a second power transistor disposed between the first node and a second node, a filter including a capacitor and an inductor, and a controller. The first power transistor is partitioned into a plurality of individually-addressable first transistor segments. The second node couples the second and fourth terminals. The second power transistor is partitioned into a plurality of individually-addressable second transistor segments. The inductor is disposed between the first node and the third terminal, and the capacitor is disposed between the third and fourth terminals.

Abstract: A switching regulator that has first, second, third and fourth terminals, a first power transistor disposed between the first terminal and a first node, a second power transistor disposed between the first node and a second node, a filter including a capacitor and an inductor, and a controller. The first power transistor is partitioned into a plurality of individually-addressable first transistor segments. The second node couples the second and fourth terminals. The second power transistor is partitioned into a plurality of individually-addressable second transistor segments. The inductor is disposed between the first node and the third terminal, and the capacitor is disposed between the third and fourth terminals.

Abstract: A RAMDAC circuit drives a display device so as display multiple modes of color depth and display resolution in a single display frame without sacrificing resolution of the higher-resolution mode, and adjusts the output pixel rate to match that of the display mode being display on a pixel-by-pixel basis. The RAMDAC circuit switches between two graphics modes on-the-fly on a pixel-by-pixel basis in accordance with mode control bits stored in the pixel data. Furthermore, the RAMDAC circuit switches between two output pixel rates such that the amount of video memory used for any predefined screen area remains constant even though the output pixel rate and resolution are dynamically adjusted.

Abstract: The noise suppression system has a discriminator, an amplitude circuit and a filtering circuit. The discriminator has an input sensor, a timer and a decision unit. The input sensor senses when the incoming signal is over a given amplitude threshold and starts the timer running. The decision unit determines when the time is over a given time threshold and the discriminator informs the amplitude circuit. The amplitude circuit has an amplitude sensor and a control unit. The amplitude sensor senses the amplitude of the incoming signal when the discriminator has a signal over the given time threshold and the amplitude sensor relays the amplitude to the control unit. The control unit outputs a control signal. The control unit has two amplitude thresholds, the control signal being at a constant minimum below the first threshold, proportional to the amplitude sensor amplitude between the thresholds, and at a constant maximum above the second threshold.

Abstract: The temperature compensated reference circuit has a first common emitter BJT whose base is connected to a first JFET current source and through a JFET resistor to a voltage output. The JFET resistor is biased in the linear region and the JFET current source is biased in the saturation region in an operating condition. The voltage across the JFET resistor is selected to be approximately equal to the pinch-off voltage of the JFET current source. The temperature co-efficient of the first BJT and JFET resistor will cancel one another to produce a generally temperature invariant voltage at the output. The voltage regulator incorporates the reference circuit and has a second BJT current source driving the reference circuit. A feedback system includes a second JFET current source between the collector of the first BJT and the connection between the voltage output and the collector of the second BJT. The second JFET current source drives the base of a common emitter third BJT.