Abstract: Systems and methods are provided for testing a Device Under Test (DUT) in its working environment. A control computer is coupled to an air compressor and generates a temperature control signal that is provided to the air compressor to generate an amount of hot air or cold air to set the temperature of the DUT's working environment to a desired test temperature. The control computer also generates at least one test signal that is sent to a hardware test element for testing at least one memory component of the DUT at the desired test temperature and obtaining test results. The control computer analyzes the test results to determine a parameter adjustment for the at least one memory element so that it operates in a stable manner at the test temperature.

Abstract: Systems and methods are provided for testing a Device Under Test (DUT) in its working environment. A control computer is coupled to an air compressor and generates a temperature control signal that is provided to the air compressor to generate an amount of hot air or cold air to set the temperature of the DUT's working environment to a desired test temperature. The control computer also generates at least one test signal that is sent to a hardware test element for testing at least one memory component of the DUT at the desired test temperature and obtaining test results. The control computer analyzes the test results to determine a parameter adjustment for the at least one memory element so that it operates in a stable manner at the test temperature.

Abstract: Embodiments described herein relate to systems and methods for testing and assembling memory modules. In at least one embodiment, the method comprises: assembling a memory module, the memory module comprising at least one memory device having one or more defective memory locations; wherein the assembling comprises storing the data that identifies the one or more defective memory locations on the memory device in a persistent store on the memory module, wherein the memory module comprises a microprocessor and persistent memory associated with the microprocessor, and wherein the persistent store on the memory module comprises the persistent memory associated with the microprocessor.

Abstract: Embodiments of a system and method for testing an integrated circuit device are described herein. Testing is complemented by a determination of characteristics of a data valid window that identifies components of a response data signal from a device under test where the data signal can always be expected to be stable.

Abstract: Embodiments described herein relate to systems and methods for testing and assembling memory modules. In at least one embodiment, the method comprises: assembling a memory module, the memory module comprising at least one memory device having one or more defective memory locations; wherein the assembling comprises storing the data that identifies the one or more defective memory locations on the memory device in a persistent store on the memory module, wherein the memory module comprises a microprocessor and persistent memory associated with the microprocessor, and wherein the persistent store on the memory module comprises the persistent memory associated with the microprocessor.

Abstract: Embodiments described herein relate to systems and methods for testing and assembling memory modules. In at least one embodiment, the method comprises, for each memory device of a plurality of memory devices, based on testing performed on the memory device, determining whether the memory device has any defective memory locations, and if so, identifying the one or more defective memory locations, and generating data that identifies the one or more defective memory locations on the memory device; and assembling a memory module comprising at least one memory device having one or more defective memory locations; wherein the assembling comprises, for each memory device of the memory module having one or more defective memory locations, storing the data that identifies the one or more defective memory locations on the memory device in a persistent store on the memory module.

Abstract: Embodiments described herein relate to systems and methods for testing and assembling memory modules. In at least one embodiment, the method comprises, for each memory device of a plurality of memory devices, based on testing performed on the memory device, determining whether the memory device has any defective memory locations, and if so, identifying the one or more defective memory locations, and generating data that identifies the one or more defective memory locations on the memory device; and assembling a memory module comprising at least one memory device having one or more defective memory locations; wherein the assembling comprises, for each memory device of the memory module having one or more defective memory locations, storing the data that identifies the one or more defective memory locations on the memory device in a persistent store on the memory module.

Abstract: A testing apparatus for analyzing a memory module under test operating within an application system, wherein the memory module under test is coupled to a processor of the application system, is disclosed herein. In at least one embodiment, the testing apparatus comprises a first interface for coupling to the application system, a second interface for coupling to a reference memory module, a controller coupled to the first and second interfaces, at least one comparator, and a data logging unit. The data logging unit is configured to receive logging data from the controller and at least one test result from the at least one comparator, and to record, in a memory, at least a subset of the logging data, such that more specific details of memory errors revealed during behavioral testing of memory modules may be identified, examined, and stored for subsequent analysis.

Abstract: Embodiments of a system and method for testing an integrated circuit device are described herein. Testing is complemented by a determination of characteristics of a data valid window that identifies components of a response data signal from a device under test where the data signal can always be expected to be stable.

Abstract: A testing apparatus for analyzing a memory module under test operating within an application system, wherein the memory module under test is coupled to a processor of the application system, is disclosed herein. In at least one embodiment, the testing apparatus comprises a first interface for coupling to the application system, a second interface for coupling to a reference memory module, a controller coupled to the first and second interfaces, at least one comparator, and a data logging unit. The data logging unit is configured to receive logging data from the controller and at least one test result from the at least one comparator, and to record, in a memory, at least a subset of the logging data, such that more specific details of memory errors revealed during behavioral testing of memory modules may be identified, examined, and stored for subsequent analysis.

Abstract: Embodiments described herein relate to systems and methods for testing integrated circuit devices within an environment that is representative of the application environment in which an integrated circuit device will be used. In at least one embodiment, the testing system comprises a second reference integrated circuit device that provides flexibility in testing, allowing only the input to a first reference integrated circuit device of an application system to be tapped and not necessarily both input to and output from the first reference integrated circuit device to be tapped. In some embodiments, the input to the first reference integrated circuit device may be subsequently modified by a controller.

Abstract: Embodiments described herein relate to systems and methods for testing integrated circuit devices within an environment that is representative of the application environment in which an integrated circuit device will be used.

Abstract: Embodiments of an apparatus and method for high-speed testing of a device under test are described herein, where the device under test is coupled to a tester via a limited passband communication channel. A plurality of test vector patterns is generated having characteristics such that when a given test vector pattern is transmitted electrically at a transmission rate via the communication channel, the test vector pattern has a frequency content that is less than the frequency content of a high frequency test vector pattern if the high frequency test vector pattern were to be transmitted electrically at the transmission rate via the communication channel, and such that the frequency content of each test vector pattern when transmitted electrically at the transmission rate via the communication channel falls within the passband associated with the communication channel.

Abstract: Embodiments of an apparatus and method for high-speed testing of a device under test are described herein, where the device under test is coupled to a tester via a limited passband communication channel. A plurality of test vector patterns is generated having characteristics such that when a given test vector pattern is transmitted electrically at a transmission rate via the communication channel, the test vector pattern has a frequency content that is less than the frequency content of a high frequency test vector pattern if the high frequency test vector pattern were to be transmitted electrically at the transmission rate via the communication channel, and such that the frequency content of each test vector pattern when transmitted electrically at the transmission rate via the communication channel falls within the passband associated with the communication channel.