Abstract: A high-speed serrodyne digital frequency translator utilizes a digital phase-shifter, for example, of series coupled Schiffman type cells, which have reference and delay paths which are switched by three-terminal devices of the gallium arsenide FET type. No bias voltages are used and the FETS are driven by the output of a binary divider network which in turn is composed of GaAs FETS as active elements. Thus switching in the picosecond range results.

Abstract: An electronic phase shifter utilizes a serrodynable digital phase shifter which is driven by the output of a multi-bit counter. The counter in turn has its clock input driven by a pulse train which produces the desired frequency translation for noise and deception jamming. Alternatively, the counter has jam inputs for electronic antenna steering and electronic phase shift applications. In order to compensate for step phase error which causes undesirable spurious sidebands, the cells of the phase shifter are pretested for individual phase errors and an interface memory is provided which by use of a corrected counter code minimizes the errors.