Abstract: A phase alignment device for alignment of phase between a data signal and a clock signal is described. The phase alignment device includes a signal generator generating an enable signal configured to control shifting of the data signal through an external data buffering device, a reference signal module generating phase reference signals based on the clock signal, the phase reference signals differing in phase from one another, and a data sampler identifying a reference point in the data signal. The phase alignment device further includes a phase capture module identifying one of the phase reference signals closest in phase to the reference point in the data signal as a selected phase reference signal.

Abstract: A processor is described that includes a plurality of registers configured as a status stack. The processor is configured to sequentially store results from status producing instruction executions in the status stack and implement a branching instruction based on at least one of the stored results.

Abstract: A multiprocessing apparatus includes a memory and a plurality (M) of processors coupled to share the memory. Access to the memory is time-division multiplexed among the plurality of processors. In one embodiment, a selected processor retrieves M words of instruction forming K instructions during a given clock cycle. The selected processor executes M-K NOP instructions if K<M.