Abstract: A method for minimizing a test set for optimal coverage is disclosed. The method includes generating a first test set which is both an empty and minimal test set. Then, generating a second test set with a predetermined number of tests. Further, partitioning the second test set into a control test set and an experiment test set. Subsequently, providing a list of tests for coverage by merging the control test set with the first test set to form a merged list of sets.

Abstract: Described herein is a system having a multi-host Ethernet controller (102) configured to provide communication and control between two or more independent host processors (104) and a network device. In one implementation, the multi host Ethernet controller (102), having an integrated L2 switch (110) to enable a plurality of independent host systems to access same physical gigabit network port concurrently. Each host processor (104) sees the controller as PCI based independent network controller and accesses the controller using its own mini-port driver. The common programming parameters such as Link Speed or Inter Packet Gap (IPG) are programmed by a virtualization engine. Packets from network (LAN) are switched based on MAC destination address and sent to corresponding host based on MAC destination address. Packets from each host processor (104) are forwarded to network interface or other host processor (104) based on MAC destination address.

Abstract: A method for minimizing a test set for optimal coverage is disclosed. The method includes generating a first test set which is both an empty and minimal test set. Then, generating a second test set with a predetermined number of tests. Further, partitioning the second test set into a control test set and an experiment test set. Subsequently, providing a list of tests for coverage by merging the control test set with the first test set to form a merged list of sets.

Abstract: Described herein is a system having a multi-host Ethernet controller (102) configured to provide communication and control between two or more independent host processors (104) and a network device. In one implementation, the multi host Ethernet controller (102), having an integrated L2 switch (110) to enable a plurality of independent host systems to access same physical gigabit network port concurrently. Each host processor (104) sees the controller as PCI based independent network controller and accesses the controller using its own mini-port driver. The common programming parameters such as Link Speed or Inter Packet Gap (IPG) are programmed by a virtualization engine. Packets from network (LAN) are switched based on MAC destination address and sent to corresponding host based on MAC destination address. Packets from each host processor (104) are forwarded to network interface or other host processor (104) based on MAC destination address.