Abstract: A system and method of mapping a host computer address space into a network interface adapter (NIA) address space. A network interface processor within the NIA requests a memory allocation from the host computer. The host computer responds with an assigned base address in the host computer address space, and a length defining the contiguous addresses within the host computer address space equal to the allocation requested by the NIA processor. A hardware trap is set such that an interrupt to the NIA processor is generated when the host computer attempts to access data at an address within the allocated address range of host computer contiguous addresses. The network interface processor translates the received host address to a physical address within the NIA address space, reads the data at the respective NIA physical address, and transfers the data to the host computer.

Abstract: A system and method of mapping a host computer address space into a network interface adapter (NIA) address space. A network interface processor within the NIA requests a memory allocation from the host computer. The host computer responds with an assigned base address in the host computer address space, and a length defining the contiguous addresses within the host computer address space equal to the allocation requested by the NIA processor. A hardware trap is set such that an interrupt to the NIA processor is generated when the host computer attempts to access data at an address within the allocated address range of host computer contiguous addresses. The network interface processor translates the received host address to a physical address within the NIA address space, reads the data at the respective NIA physical address, and transfers the data to the host computer.

Abstract: The present application is directed to a method and system for mapping a host computer address space into a network interface adapter (NIA) address space. A network interface processor contained within the NIA requests a memory allocation from the host computer. The host computer responds with an assigned base address in the host computer address space and a length defining the contiguous addresses within the host computer address space equal to the allocation requested by the NIA processor. A hardware trap is set, such that, an interrupt to the NIA processor is generated when the host computer attempts to access data at an address within the allocated address range of host computer contiguous addresses. The network interface processor translates the received host address to a physical address within the NIA address space, reads the data at the respective NIA physical address and transfers the data to the host computer.

Abstract: A multi-mode network interface adapter includes a diagnostic mode, a sleep mode and a run-time mode. The network adapter enters the diagnostic mode at least in response to a power-up signal and validates the operation of predetermined network adapter functions. In the sleep mode, the network adapter transmits messages onto the network and responds to messages received from the network that would otherwise be handled by a host computer operating system. In this mode, the network adapter creates the appearance to other devices that the host computer is operational even if the host computer has entered a reduced power state in which the host computer operating system is not operational. In the run-time mode, the network adapter passes messages received from the network to the host computer and transmits messages received from the host computer over the network.

Abstract: A method and apparatus for implementing a self-diagnostic capability in a network interface adapter in which failure data is provided to a host processor. The host processor may report the failure data to a user or additionally the host processor may attempt to correct predetermined faults in code images by writing a valid code image to a memory on the network interface adapter.