Abstract: Conductive clip connection arrangements for semiconductor packages are disclosed. Some examples provide electrically conductive clip connection arrangements for semiconductor packages that improve electrical performance and fabrication reliability while maintaining compatibility with existing quality control processes. Some examples provide innovative conductive clip structures and die pad arrangements that broaden the range of options available for tailoring the physical configurations of one or more of the constituent conductive clips and/or die pads to achieve specific electrical performance targets.

Abstract: Conductive clip connection arrangements for semiconductor packages are disclosed. Some examples provide electrically conductive clip connection arrangements for semiconductor packages that improve electrical performance and fabrication reliability while maintaining compatibility with existing quality control processes. Some examples provide innovative conductive clip structures and die pad arrangements that broaden the range of options available for tailoring the physical configurations of one or more of the constituent conductive clips and/or die pads to achieve specific electrical performance targets.

Abstract: Conductive clip connection arrangements for semiconductor packages are disclosed. Some examples provide electrically conductive clip connection arrangements for semiconductor packages that improve electrical performance and fabrication reliability while maintaining compatibility with existing quality control processes. Some examples provide innovative conductive clip structures and die pad arrangements that broaden the range of options available for tailoring the physical configurations of one or more of the constituent conductive clips and/or die pads to achieve specific electrical performance targets.

Abstract: Conductive clip connection arrangements for semiconductor packages are disclosed. Some examples provide electrically conductive clip connection arrangements for semiconductor packages that improve electrical performance and fabrication reliability while maintaining compatibility with existing quality control processes. Some examples provide innovative conductive clip structures and die pad arrangements that broaden the range of options available for tailoring the physical configurations of one or more of the constituent conductive clips and/or die pads to achieve specific electrical performance targets.

Abstract: Die stacking systems and methods are disclosed. In an embodiment, a semiconductor device includes a passivation surface and a conductive die receiving surface located in an opening of the passivation surface. The conductive die receiving surface has a surface area that is larger than a footprint of a second die that is electrically coupled to the conductive die receiving surface.

Abstract: An IC package includes ground paddle(s), power paddle(s), a lead frame, a die, and electrically conductive input/output circuit pads, ground circuit pads, and bond wires. The lead frame may include input/output (I/O) pads positioned near the perimeter of the lead frame and around the ground paddle(s) and power paddle(s). The die may be positioned on one of the ground paddles and may include die terminals. Each I/O circuit pad may be positioned on and connected with one of the I/O pads. The ground circuit pads may be positioned on said one ground paddle around the die between the die and the I/O circuit pads. Each ground circuit pad may be connected to said one ground paddle. Each bond wire may connect a die terminal to an I/O circuit pad and/or a ground circuit pad. A bond wire may connect a die terminal to a power paddle.

Abstract: Die stacking systems and methods are disclosed. In an embodiment, a semiconductor device includes a passivation surface and a conductive die receiving surface located in an opening of the passivation surface. The conductive die receiving surface has a surface area that is larger than a footprint of a second die that is electrically coupled to the conductive die receiving surface.

Abstract: Die stacking systems and methods are disclosed. In an embodiment, a die has a surface that includes a passivation area, at least one conductive bond pad area, and a conductive stacked die receiving area sized to receive at least a second die.

Abstract: The disclosure provides integrated circuit packages including a lead frame having multiple I/O pads positioned proximate to the lead frame perimeter around a central ground paddle, an integrated circuit die having electrically conductive die terminals positioned on the central ground paddle, and multiple ground circuit pads positioned on and in electrical connection with the central ground paddle. Electrically conductive I/O circuit pads are arranged about the die between the ground circuit pads and the I/O pads, each I/O circuit pad electrically connected to one of the I/O pads. Electrically conductive bond wires connect one or more of the die terminals to one or more I/O circuit pads or one or more ground circuit pads. In certain embodiments, the disclosure further provides an integrated circuit positioned to engage the integrated circuit die in electrical connection with the die terminals. The disclosure also relates to methods of packaging an integrated circuit to reduce packaging parasitics.

Abstract: Die stacking systems and methods are disclosed. In an embodiment, a die has a surface that includes a passivation area, at least one conductive bond pad area, and a conductive stacked die receiving area sized to receive at least a second die.

Abstract: The disclosure provides integrated circuit packages including a lead frame having multiple I/O pads positioned proximate to the lead frame perimeter around a central ground paddle, an integrated circuit die having electrically conductive die terminals positioned on the central ground paddle, and multiple ground circuit pads positioned on and in electrical connection with the central ground paddle. Electrically conductive I/O circuit pads are arranged about the die between the ground circuit pads and the I/O pads, each I/O circuit pad electrically connected to one of the I/O pads. Electrically conductive bond wires connect one or more of the die terminals to one or more I/O circuit pads or one or more ground circuit pads. In certain embodiments, the disclosure further provides an integrated circuit positioned to engage the integrated circuit die in electrical connection with the die terminals. The disclosure also relates to methods of packaging an integrated circuit to reduce packaging parasitics.

Abstract: A system and method have been provided for removing high lead content solder balls from the surface of a circuit package for the purpose of rework. The invention is applicable to ball grid array (BGA), C4 balls, chip scale balls, and flip chip bumps. Advantageously, the room temperature solder ball rework procedure minimizes damage to the circuit package. Specifically, a thin-film stainless steel mask with openings to expose the solder balls, is formed over the circuit package, and the solder balls are removed in a shearing or grinding operation, leaving a solder ball residue. Then, a conventional thick mask film is formed and a solder paste is deposited to fill the apertures. The solder ball residue forms a wettable surface for the low temperature attachment of new solder balls.

Abstract: An electronic device package includes a modified ball grid array (“BGA”) interconnect substrate upon which a flip-chip device is mounted. The flip-chip device includes one or more high speed input/output solder bumps corresponding to input/output signals having data rates of up to 40 Gbps. A high speed solder bump is directly connected to an interconnect via formed within the BGA substrate, and the via is directly connected to a respective BGA solder ball positioned at an interior point of the BGA solder ball matrix. The BGA substrate is void of BGA solder balls between the designated high speed BGA solder ball and at least one edge of the substrate, thus providing a clear path to the designated high speed BGA solder ball for a high speed conductive trace formed on a printed circuit board.

Abstract: A package substrate (11) having access to a plating bus (36, 38) through intermediate routing layers (4, 6). Specifically, electrical contact between a solder pad (16, 19, 51), and its respective bond post (27), if any, is made by routing a trace (32, 52) through an intermediate routing layer (4, 6). The trace (32, 52) begins within a final package dimension (10) and extends to a peripheral portion (12) which is excised during manufacturing. There is a conductive trace (32, 52) visible from the side of the final packaged device (10').

Abstract: The present invention comprises a semiconductor device (20) having a active circuit (22) and a bond pad area (24). Within the bond pad area there are a plurality of rows of bond pads. Sets of bond pads (30-36) include one bond pad from each row. The bond pads (26) are uniquely positioned within the bond pad area (24) to allow for a first wire pitch between pads which are adjacent and in the same set, and a second wire pitch between pads which are adjacent and in different sets. A method of determining placement of the bond pads (26) is taught.

Abstract: A bond post configuration for wire bonded semiconductors has bond posts grouped in three posts where two are arranged closely to a side of a die about a first axis and a third is arranged in between and further removed from the side about a second axis. In one form, the bond post configuration is a radial configuration. Additionally, conductive traces which extend from the bond posts and away from the die are placed off-center from the the bond posts about the first axis to provide more placement area for the bond posts arranged about the second axis. The bond post configuration may be utilized in any wire bonded semiconductor.