Patents by Inventor Lay Cheng Choo

Lay Cheng Choo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250125582
    Abstract: An integrated device for optical power control and stabilization is provided. The integrated device includes a laser source and an optical amplifier operably coupled to the laser source. The laser source emits a light having a narrow optical linewidth at an initial output power. The optical amplifier, for example, a semiconductor optical amplifier, receives and amplifies the light from the laser source, and emits the amplified light. The optical amplifier controls a resultant output power of the emitted amplified light to a configurable level while maintaining the narrow optical linewidth in the emitted amplified light and a lasing wavelength of the laser source constant. Based on operation with a reverse bias, the optical amplifier also operates as an optical absorber and suppresses the received light having the narrow optical linewidth without requiring a change to a drive current of the laser source.
    Type: Application
    Filed: October 11, 2024
    Publication date: April 17, 2025
    Inventors: Yee Loy LAM, Huade SHU, Lay Cheng CHOO, Long Cheng KOH, Yuen Chuen CHAN
  • Patent number: 12149044
    Abstract: An optoelectronic device includes a semiconductor die that includes a substrate layer, a laser diode, first and second conducting pads, a cathode pad, an anode pad, and a passivation layer. The laser diode and the conducting pads are formed on the substrate layer. The formation of the conducting pads directly on the substrate layer offers an increased area for heat dissipation. The cathode pad is formed on the first conducting pad whereas the anode pad is formed above the second conducting pad. The passivation layer is formed above the laser diode. The attachment of the semiconductor die to a submount of the optoelectronic device occurs by way of the cathode pad and the anode pad. After the attachment, a free space is created directly between the passivation layer and the submount to reduce the impact of solder bonding stress on the laser diode.
    Type: Grant
    Filed: January 19, 2022
    Date of Patent: November 19, 2024
    Assignee: DENSELIGHT SEMICONDUCTORS PTE LTD
    Inventors: Yee Loy Lam, Hon Yuen Aaron Sim, Lay Cheng Choo, Long Cheng Koh
  • Publication number: 20220231477
    Abstract: An optoelectronic device includes a semiconductor die that includes a substrate layer, a laser diode, first and second conducting pads, a cathode pad, an anode pad, and a passivation layer. The laser diode and the conducting pads are formed on the substrate layer. The formation of the conducting pads directly on the substrate layer offers an increased area for heat dissipation. The cathode pad is formed on the first conducting pad whereas the anode pad is formed above the second conducting pad. The passivation layer is formed above the laser diode. The attachment of the semiconductor die to a submount of the optoelectronic device occurs by way of the cathode pad and the anode pad. After the attachment, a free space is created directly between the passivation layer and the submount to reduce the impact of solder bonding stress on the laser diode.
    Type: Application
    Filed: January 19, 2022
    Publication date: July 21, 2022
    Applicant: DENSELIGHT SEMICONDUCTORS PTE LTD
    Inventors: Yee Loy Lam, Hon Yuen Aaron Sim, Lay Cheng Choo, Long Cheng Koh
  • Patent number: 7037791
    Abstract: In accordance with the objects of this invention, a new method of fabricating a polysilicon gate transistor is achieved. An alternating aperture phase shift mask (AAPSM) is used to pattern polysilicon gates in a single exposure without a trim mask. A semiconductor substrate is provided. A gate dielectric layer is deposited. A polysilicon layer is deposited. The polysilicon layer, the gate dielectric layer and the semiconductor substrate are patterned to form trenches for planned shallow trench isolations (STI). A trench oxide layer is deposited filling the trenches. The trench oxide layer is polished down to the top surface of the polysilicon layer to complete the STI. A photoresist layer is deposited and patterned to form a feature mask for planned polysilicon gates. The patterning is by a single exposure using an AAPSM mask. Unwanted features in the photoresist pattern that are caused by phase conflicts overlie the STI. The polysilicon layer is etched to form the polysilicon gates.
    Type: Grant
    Filed: April 30, 2002
    Date of Patent: May 2, 2006
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Lay Cheng Choo, James Yong Meng Lee, Lap Chan
  • Patent number: 6807215
    Abstract: There is provided a semiconductor laser comprising a gain section and an adjacent Bragg section, wherein output laser light is emitted via a facet at an interface between air and the gain section, the Bragg section comprising a distributed reflecting structure having a length substantially greater than required to ensure single longitudinal mode operation of the laser in which the side-mode suppression ratio (SMSR) is 35 dB or more, thereby in use substantially suppressing optical feedback from a facet at an interface between the Bragg section and air, and wherein an interface between the Bragg section and the gain section is quantum well intermixed, thereby rendering the interface substantially anti-reflecting at the wavelength of the laser.
    Type: Grant
    Filed: October 8, 2002
    Date of Patent: October 19, 2004
    Assignee: Denselight Semiconductor PTE LTD
    Inventors: Yee Loy Lam, Yuen Chuen Chan, Teik Kooi Ong, Hwi Siong Lim, Lay Cheng Choo, Peh Wei Tan
  • Publication number: 20030203580
    Abstract: In accordance with the objects of this invention, a new method of fabricating a polysilicon gate transistor is achieved. An alternating aperture phase shift mask (AAPSM) is used to pattern polysilicon gates in a single exposure without a trim mask. A semiconductor substrate is provided. A gate dielectric layer is deposited. A polysilicon layer is deposited. The polysilicon layer, the gate dielectric layer and the semiconductor substrate are patterned to form trenches for planned shallow trench isolations (STI). A trench oxide layer is deposited filling the trenches. The trench oxide layer is polished down to the top surface of the polysilicon layer to complete the STI. A photoresist layer is deposited and patterned to form a feature mask for planned polysilicon gates. The patterning is by a single exposure using an AAPSM mask. Unwanted features in the photoresist pattern that are caused by phase conflicts overlie the STI. The polysilicon layer is etched to form the polysilicon gates.
    Type: Application
    Filed: April 30, 2002
    Publication date: October 30, 2003
    Applicant: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Lay Cheng Choo, James Yong Meng Lee, Lap Chan
  • Publication number: 20030072344
    Abstract: There is provided a semiconductor laser comprising a gain section and an adjacent Bragg section, wherein output laser light is emitted via a facet at an interface between air and the gain section, the Bragg section comprising a distributed reflecting structure having a length substantially greater than required to ensure single longitudinal mode operation of the laser in which the side-mode suppression ratio (SMSR) is 35 dB or more, thereby in use substantially suppressing optical feedback from a facet at an interface between the Bragg section and air, and wherein an interface between the Bragg section and the gain section is quantum well intermixed, thereby rendering the interface substantially anti-reflecting at the wavelength of the laser.
    Type: Application
    Filed: October 8, 2002
    Publication date: April 17, 2003
    Inventors: Yee Loy Lam, Yuen Chuen Chan, Teik Kooi Ong, Hwi Siong Lim, Lay Cheng Choo, Peh Wei Tan