Patents by Inventor Lay Yeap Lim
Lay Yeap Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9728492Abstract: A strip of semiconductor devices includes a plurality of leadframes electrically isolated from each other, a plurality of semiconductor chips, and an encapsulation material. Each leadframe has a first surface and a second surface opposite to the first surface. At least one semiconductor chip of the plurality of semiconductor chips is electrically coupled to the first surface of each leadframe. The encapsulation material encapsulates each semiconductor chip and at least portions of each leadframe.Type: GrantFiled: May 24, 2016Date of Patent: August 8, 2017Assignee: Infineon Technologies AGInventors: Thiong Zhou See, Wee Boon Tay, Lay Yeap Lim
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Patent number: 9303327Abstract: A system, a packaged component and a method for making a packaged component are disclosed. In an embodiment a system comprises a component carrier, a component disposed on the component carrier and an insulating layer disposed on an electrically conductive surface of at least one of the component carrier or the component, wherein the insulating layer comprises a polymer and an inorganic material comprising a dielectric strength of equal or greater than 15 ac-kv/mm and a thermal conductivity of equal or greater than 15 W/m*K.Type: GrantFiled: January 10, 2013Date of Patent: April 5, 2016Assignee: Infineon Technologies AGInventors: Sung Hoe Yeong, Lay Yeap Lim, Tien Shyang Law
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Patent number: 9263419Abstract: A lead frame strip includes connected unit lead frames each having a die paddle, a tie bar directly connecting the die paddle to a periphery of the unit lead frame, leads directly connected to the periphery of the unit lead frame and projecting toward the die paddle, and an opening in the periphery adjacent the tie bar. The openings in the periphery of the unit lead frames are spanned with an electrically insulating material that connects the tie bar of each unit lead frame to the periphery of the unit lead frame. The direct connections between the tie bars and the periphery of the unit lead frames are severed prior to subsequent processing, so that the tie bars remain connected to the periphery of the unit lead frames by the electrically insulating material and the die paddles are electrically disconnected from the periphery of the unit lead frames.Type: GrantFiled: August 30, 2013Date of Patent: February 16, 2016Assignee: Infineon Technologies AGInventors: Nee Wan Khoo, Lay Yeap Lim
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Patent number: 9252063Abstract: A leadframe strip includes a plurality of unit leadframes connected to a periphery of the leadframe strip, each unit leadframe having a die paddle, a plurality of leads and a semiconductor die attached to the die paddle. The leadframe strip is tested by electrically isolating at least the leads from the periphery of the leadframe strip such that at least some of the leads extend uninterrupted beyond a final lead outline of the unit leadframes after electrical isolation from the periphery of the leadframe strip. The semiconductor dies are tested, which includes probing the die paddles and the leads that extend uninterrupted beyond the final lead outline of the unit leadframes after electrical isolation from the periphery of the leadframe strip. The unit leadframes are severed from the leadframe strip along the final lead outline of the unit leadframes after testing the semiconductor dies.Type: GrantFiled: July 7, 2014Date of Patent: February 2, 2016Assignee: Infineon Technologies AGInventors: Nee Wan Khoo, Lay Yeap Lim, Tian San Tan
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Publication number: 20160005663Abstract: A leadframe strip includes a plurality of unit leadframes connected to a periphery of the leadframe strip, each unit leadframe having a die paddle, a plurality of leads and a semiconductor die attached to the die paddle. The leadframe strip is tested by electrically isolating at least the leads from the periphery of the leadframe strip such that at least some of the leads extend uninterrupted beyond a final lead outline of the unit leadframes after electrical isolation from the periphery of the leadframe strip. The semiconductor dies are tested, which includes probing the die paddles and the leads that extend uninterrupted beyond the final lead outline of the unit leadframes after electrical isolation from the periphery of the leadframe strip. The unit leadframes are severed from the leadframe strip along the final lead outline of the unit leadframes after testing the semiconductor dies.Type: ApplicationFiled: July 7, 2014Publication date: January 7, 2016Inventors: Nee Wan Khoo, Lay Yeap Lim, Tian San Tan
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Patent number: 9159656Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.Type: GrantFiled: September 5, 2013Date of Patent: October 13, 2015Assignee: Fairchild Semiconductor CorporationInventors: Oseob Jeon, Yoonhwa Choi, Boon Huan Gooi, Maria Cristina B. Estacio, David Chong, Tan Teik Keng, Shibaek Nam, Rajeev Joshi, Chung-Lin Wu, Venkat Iyer, Lay Yeap Lim, Byoung-Ok Lee
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Publication number: 20150064849Abstract: A lead frame strip includes connected unit lead frames each having a die paddle, a tie bar directly connecting the die paddle to a periphery of the unit lead frame, leads directly connected to the periphery of the unit lead frame and projecting toward the die paddle, and an opening in the periphery adjacent the tie bar. The openings in the periphery of the unit lead frames are spanned with an electrically insulating material that connects the tie bar of each unit lead frame to the periphery of the unit lead frame. The direct connections between the tie bars and the periphery of the unit lead frames are severed prior to subsequent processing, so that the tie bars remain connected to the periphery of the unit lead frames by the electrically insulating material and the die paddles are electrically disconnected from the periphery of the unit lead frames.Type: ApplicationFiled: August 30, 2013Publication date: March 5, 2015Inventors: Nee Wan Khoo, Lay Yeap Lim
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Publication number: 20140192500Abstract: A system, a packaged component and a method for making a packaged component are disclosed. In an embodiment a system comprises a component carrier, a component disposed on the component carrier and an insulating layer disposed on an electrically conductive surface of at least one of the component carrier or the component, wherein the insulating layer comprises a polymer and an inorganic material comprising a dielectric strength of equal or greater than 15 ac-kv/mm and a thermal conductivity of equal or greater than 15 W/m*K.Type: ApplicationFiled: January 10, 2013Publication date: July 10, 2014Applicant: INFINEON TECHNOLOGIES AGInventors: Sung Hoe Yeong, Lay Yeap Lim, Tien Shyang Law
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Publication number: 20140167238Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.Type: ApplicationFiled: September 5, 2013Publication date: June 19, 2014Applicant: FAIRCHILD SEMICONDUCTOR CORPORATIONInventors: Oseob Jeon, Yoonhwa Choi, Boon Huan Gooi, Maria Cristina B. Estacio, David Chong, Tan Teik Keng, Shibaek Nam, Rajeev Joshi, Chung-Lin Wu, Venkat Iyer, Lay Yeap Lim, Byoung-Ok Lee
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Patent number: 8664752Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.Type: GrantFiled: March 26, 2012Date of Patent: March 4, 2014Assignee: Fairchild Semiconductor CorporationInventors: Oseob Jeon, Yoonhwa Choi, Boon Huan Gooi, Maria Cristina B. Estacio, David Chong, Tan Teik Keng, Shibaek Nam, Rajeev Joshi, Chung-Lin Wu, Venkat Iyer, Lay Yeap Lim, Byoung-Ok Lee
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Publication number: 20120181675Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.Type: ApplicationFiled: March 26, 2012Publication date: July 19, 2012Inventors: Oseob Jeon, Yoonhwa Choi, Boon Huan Gooi, Maria Cristina B. Estacio, David Chong, Tan Teik Keng, Shibaek Nam, Rajeev Joshi, Chung-Lin Wu, Venkat Iyer, Lay Yeap Lim, Byoung-Ok Lee
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Patent number: 8110447Abstract: A lead frame with patterned conductive runs on the top surface to accept a wire bonded or flip-chip or COL configuration is disclosed. The top pattern is completed and the bottom is etched away creating cavities. The cavities are filled with a pre-mold material that lend structural support of the lead frame. The top is then etch through the lead frame to the pre-mold, except with the top conductive runs exist. In this manner the conductive runs are completed and isolated from each other so that the placement of the runs is flexible. The chips are mounted and the encapsulated and the lead frames are singulated. The pattern on the top and the bottom may be defined by first plated the patterns desired.Type: GrantFiled: March 21, 2008Date of Patent: February 7, 2012Assignee: Fairchild Semiconductor CorporationInventors: Lay Yeap Lim, David Chong
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Patent number: 7923301Abstract: A leadframe structure is disclosed. The leadframe structure includes a first leadframe structure portion with a first thin portion and a first thick portion, where the first thin portion is defined in part by a first recess. It also includes a second leadframe structure portion with a second thin portion and a second thick portion, where the second thin portion is defined in part by a second recess. The first thin portion faces the second recess, and the second thin portion faces the first recess.Type: GrantFiled: February 3, 2010Date of Patent: April 12, 2011Assignee: Fairchild Semiconductor CorporationInventor: Lay Yeap Lim
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Publication number: 20100258925Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.Type: ApplicationFiled: June 25, 2010Publication date: October 14, 2010Inventors: Oseob Jeon, Yoonhwa Choi, Boon Huan Gooi, Maria Cristina B. Estacio, David Chong, Tan Teik Keng, Shibaek Nam, Rajeev Joshi, Chung-Lin Wu, Venkat Iyer, Lay Yeap Lim, Byoung-Ok Lee
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Publication number: 20100136750Abstract: A leadframe structure is disclosed. The leadframe structure includes a first leadframe structure portion with a first thin portion and a first thick portion, where the first thin portion is defined in part by a first recess. It also includes a second leadframe structure portion with a second thin portion and a second thick portion, where the second thin portion is defined in part by a second recess. The first thin portion faces the second recess, and the second thin portion faces the first recess.Type: ApplicationFiled: February 3, 2010Publication date: June 3, 2010Inventor: Lay Yeap Lim
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Patent number: 7683463Abstract: A leadframe structure is disclosed. The leadframe structure includes a first leadframe structure portion with a first thin portion and a first thick portion, where the first thin portion is defined in part by a first recess. It also includes a second leadframe structure portion with a second thin portion and a second thick portion, where the second thin portion is defined in part by a second recess. The first thin portion faces the second recess, and the second thin portion faces the first recess.Type: GrantFiled: April 19, 2007Date of Patent: March 23, 2010Assignee: Fairchild Semiconductor CorporationInventor: Lay Yeap Lim
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Publication number: 20090236711Abstract: A lead frame with patterned conductive runs on the top surface to accept a wire bonded or flip-chip or COL configuration is disclosed. The top pattern is completed and the bottom is etched away creating cavities. The cavities are filled with a pre-mold material that lend structural support of the lead frame. The top is then etch through the lead frame to the pre-mold, except with the top conductive runs exist. In this manner the conductive runs are completed and isolated from each other so that the placement of the runs is flexible. The chips are mounted and the encapsulated and the lead frames are singulated. The pattern on the top and the bottom may be defined by first plated the patterns desired.Type: ApplicationFiled: March 21, 2008Publication date: September 24, 2009Inventors: Lay Yeap Lim, David Chong
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Publication number: 20090189261Abstract: Semiconductor packages with a reduced-height die pad and associated methods for making and using these semiconductor packages are described. The semiconductor packages include a lead frame with die pad of reduced height so the die pad has a height that is less than that of the lead frame. The semiconductor packages may comprise an isolated and/or a fused lead finger with a portion of an upper surface of the isolated lead finger that is removed to form a concavity to which one or more bond wires may be bonded. The upper surface of the isolated lead finger may be removed so the isolated lead finger has a height that is less than the height of the lead frame. And a perimeter of a bottom surface of the fused lead finger may be removed. Other embodiments are described.Type: ApplicationFiled: January 25, 2008Publication date: July 30, 2009Inventors: Lay Yeap Lim, David Chong
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Publication number: 20080258272Abstract: A leadframe structure is disclosed. The leadframe structure includes a first leadframe structure portion with a first thin portion and a first thick portion, where the first thin portion is defined in part by a first recess. It also includes a second leadframe structure portion with a second thin portion and a second thick portion, where the second thin portion is defined in part by a second recess. The first thin portion faces the second recess, and the second thin portion faces the first recess.Type: ApplicationFiled: April 19, 2007Publication date: October 23, 2008Inventor: Lay Yeap Lim