Patents by Inventor Lazar Bivolarski

Lazar Bivolarski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100066748
    Abstract: An efficient method and device for the parallel processing of multimedia data. Blocks (or portions thereof) are transmitted to various parallel processors, in the order of their dependency data. Earlier blocks are sent to the parallel processors first, with later blocks sent later. The blocks are stored in the parallel processors in specific locations, and shifted around as necessary, so that every block, when it is processed, has its dependency data located in a specific set of earlier blocks with specified relative positions. In this manner, its dependency data can be retrieved with the same commands. That is, earlier blocks are shifted around so that later blocks can be processed with a single set of commands that instructs each processor to retrieve its dependency data from specific known relative locations that do not vary.
    Type: Application
    Filed: July 10, 2009
    Publication date: March 18, 2010
    Inventors: Lazar Bivolarski, Bogdan Mitu
  • Publication number: 20080055307
    Abstract: A method and system of processing graphics data using fine-grain instruction parallelism is provided. The method includes geometrically processing a three dimensional data set with an integral parallel machine to produce a two dimensional geometry. The integral parallel machine can include a data parallel system and a time parallel system coupled with a memory and an input-output system. The two dimensional geometry can be rendered for reproduction on an imaging apparatus using the data parallel system. The system can comprise an array of processing elements configured for receiving fine-grained instructions. The two dimensional geometry can be mapped into the processing elements. Fine-grain instructions of the processing elements can be used in processing the graphics data and can be stored in instruction sequencers of the processing elements. A diagonal mapping scheme can be use to load the fine-grain instructions in a data memory of the processing elements in a diagonal order.
    Type: Application
    Filed: August 30, 2007
    Publication date: March 6, 2008
    Inventor: Lazar Bivolarski
  • Publication number: 20080059467
    Abstract: A method and system of processing multimedia data is provided. The method includes associating a constant identifier with a current block of the multimedia data. A frame of blocks of the multimedia data, including streaming video data, can be sorted based on the identifier. The identifier of the current block can be compared with the sorted frame of blocks and a compare condition can comprise matching a constant component of the compared blocks. A plurality of fine-grained instructions of a searching algorithm can be used in the comparing of the blocks. The plurality of fined-grained instructions can be stored in a data parallel system. Motion vectors can be generated for the frame of blocks. The generated motion vectors can also be sorted following generation of the motion vectors. A current picture can be reconfigured according to the generated motion vectors for the frame of blocks of the multimedia data.
    Type: Application
    Filed: September 4, 2007
    Publication date: March 6, 2008
    Inventor: Lazar Bivolarski
  • Publication number: 20080059762
    Abstract: The present invention is a data parallel system which is able to utilize a very high percentage of processing elements. In an embodiment, the data parallel system includes an array of processing elements and multiple instruction sequencers. Each instruction sequencer is coupled to the array of processing elements by a bus and is able to send an instruction to the array of processing elements. The processing elements are separated into classes and only execute instructions that are directed to their class, although all of the processing elements receive each instruction. In another embodiment, the data parallel system includes an array of processing elements and an instruction sequencer where the instruction sequencer is able to send multiple instructions. Again, the processing elements are separated in classes and execute instructions based on their class.
    Type: Application
    Filed: August 30, 2007
    Publication date: March 6, 2008
    Inventors: Bogdan Mitu, Gheorghe Stefan, Lazar Bivolarski
  • Publication number: 20080059763
    Abstract: A method and system of processing compressed multimedia data using fine-grain instruction parallelism is provided. The method of processing multimedia data includes transferring an instruction from each of a plurality of sequencers to associated processing elements within an array of processing elements. The instructions can be processed by the array of processing elements using fine-grain instruction parallelism. A selection mechanism using selection instructions can select the associated processing elements. The plurality of sequencers comprise fine-grain instructions for decoding the compressed multimedia data. A system for multimedia data processing includes a data parallel system which can include an array of processing elements. A plurality of sequencers are coupled to the array of processing elements. A direct memory access component is coupled to the array of processing elements. A diagonal mapping scheme can be used in transferring instructions and data to the processing elements.
    Type: Application
    Filed: August 30, 2007
    Publication date: March 6, 2008
    Inventor: Lazar Bivolarski
  • Publication number: 20070188505
    Abstract: An efficient method and device for the parallel processing of multimedia data. Blocks (or portions thereof) are transmitted to various parallel processors, in the order of their dependency data. Earlier blocks are sent to the parallel processors first, with later blocks sent later. The blocks are stored in the parallel processors in specific locations, and shifted around as necessary, so that every block, when it is processed, has its dependency data located in a specific set of earlier blocks with specified relative positions. In this manner, its dependency data can be retrieved with the same commands. That is, earlier blocks are shifted around so that later blocks can be processed with a single set of commands that instructs each processor to retrieve its dependency data from specific known relative locations that do not vary.
    Type: Application
    Filed: January 10, 2007
    Publication date: August 16, 2007
    Inventors: Lazar Bivolarski, Bogdan Mitu
  • Publication number: 20070189618
    Abstract: An efficient method and device for the parallel processing of sub-blocks of data. A parallel processing array has computing elements configured to process blocks of data of an image in a parallel manner. Blocks of image data are generated, wherein each of the blocks of image data are divided into sub-blocks, with a first data point of each sub-block flagging a beginning position of the sub-block. A block of type data is generated for each of the blocks of image data. Each of the blocks of type data contains the first data point for all of the sub-blocks in the block of image data, so that the numbers and locations of all sub-blocks in each block of image data can be determined without first having to process the block of image data.
    Type: Application
    Filed: January 10, 2007
    Publication date: August 16, 2007
    Inventors: Lazar Bivolarski, Bogdan Mitu
  • Publication number: 20070162722
    Abstract: An efficient method and device for the parallel processing of data variables. A parallel processing array has computing elements configured to process data variables in parallel. An algorithm for a plurality of computing elements of a parallel processor is loaded. The algorithm includes a plurality of processing steps. Each of the plurality of computing elements is configured to process a data variable associated with the computing element. Selection codes for the plurality of computing elements of the parallel processor are loaded, wherein the selection codes identify which of the algorithm steps are to be applied by the computing elements to the data variables. The algorithm processing steps are applied to the data variables by the computing elements, wherein for each computing element, only those processing steps identified by the selection codes are applied to the data variable.
    Type: Application
    Filed: January 10, 2007
    Publication date: July 12, 2007
    Inventors: Lazar Bivolarski, Bogdan Mitu