Patents by Inventor Le Lv

Le Lv has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230323117
    Abstract: A polymerizable liquid that can be used for producing three-dimensional objects by methods of additive manufacturing is disclosed. The polymerizable liquid may comprise: (a) a blocked or reactively blocked polyurethane prepolymer; (b) (optional) a reactive diluent; (c) a blocked or reactively blocked curing agent; (d) a photoinitiator; and (e) (optional) a blocked or reactively blocked diisocyanate. The method using such polymerizable liquid to form three-dimensional objects is also described.
    Type: Application
    Filed: June 12, 2023
    Publication date: October 12, 2023
    Applicant: LUXCREO (BEIJING) INC.
    Inventors: Guang ZHU, Yisi LU, Jie GAO, Le LV
  • Patent number: 11713395
    Abstract: A polymerizable liquid that can be used for producing three-dimensional objects by methods of additive manufacturing is disclosed. The polymerizable liquid may comprise: (a) a blocked or reactively blocked polyurethane prepolymer; (b) (optional) a reactive diluent; (c) a blocked or reactively blocked curing agent; (d) a photoinitiator; and (e) (optional) a blocked or reactively blocked diisocyanate. The method using such polymerizable liquid to form three-dimensional objects is also described.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: August 1, 2023
    Assignee: LUXCREO (BEIJING) INC.
    Inventors: Guang Zhu, Yisi Lu, Jie Gao, Le Lv
  • Patent number: 10991572
    Abstract: The present disclosure discloses a manufacturing method for a semiconductor apparatus, and relates to the field of semiconductor technologies. Forms of the method include: providing a semiconductor structure, where the semiconductor structure includes: a substrate and an interlayer dielectric layer on the substrate, where the interlayer dielectric layer has an opening for forming a gate; depositing a gate metal layer on the semiconductor structure to fill the opening, where the gate metal layer contains impurity; forming an impurity adsorption layer on the gate metal layer; performing a first annealing treatment on a semiconductor structure on which the impurity adsorption layer has been formed, to make the impurity in the gate metal layer enter the impurity adsorption layer; and removing the impurity adsorption layer after the first annealing treatment is performed.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: April 27, 2021
    Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International Corporation
    Inventors: Jin E Liang, Le Lv
  • Publication number: 20200392332
    Abstract: A polymerizable liquid that can be used for producing three-dimensional objects by methods of additive manufacturing is disclosed. The polymerizable liquid may comprise: (a) a blocked or reactively blocked polyurethane prepolymer; (b) (optional) a reactive diluent; (c) a blocked or reactively blocked curing agent; (d) a photoinitiator; and (e) (optional) a blocked or reactively blocked diisocyanate. The method using such polymerizable liquid to form three-dimensional objects is also described.
    Type: Application
    Filed: August 21, 2020
    Publication date: December 17, 2020
    Applicant: 3D-FAB LIMITED
    Inventors: Guang ZHU, Yisi LU, Jie GAO, Le LV
  • Publication number: 20190057861
    Abstract: The present disclosure discloses a manufacturing method for a semiconductor apparatus, and relates to the field of semiconductor technologies. Forms of the method include: providing a semiconductor structure, where the semiconductor structure includes: a substrate and an interlayer dielectric layer on the substrate, where the interlayer dielectric layer has an opening for forming a gate; depositing a gate metal layer on the semiconductor structure to fill the opening, where the gate metal layer contains impurity; forming an impurity adsorption layer on the gate metal layer; performing a first annealing treatment on a semiconductor structure on which the impurity adsorption layer has been formed, to make the impurity in the gate metal layer enter the impurity adsorption layer; and removing the impurity adsorption layer after the first annealing treatment is performed.
    Type: Application
    Filed: July 25, 2018
    Publication date: February 21, 2019
    Applicants: Semiconductor Manufacturing International (Shanghai)) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Jin E Liang, Le Lv