Abstract: Hold time methods, systems, and computer program products are implemented to ensure that storage elements in a circuit have sufficient hold times without detrimentally affecting cycle times for other paths in the circuit. Electric circuits are designed by determining which storage elements have hold-time deficiencies, and by inserting an appropriate time delay element in a selected path preceding the storage element, or at a source or destination storage element, without exceeding a predetermined cycle time in a second path that overlaps the first path, for at least one storage element in an electrical circuit. The invention simulates insertion of the time delay element before or after a logic element that precedes a storage element that has a hold-time deficiency.