Abstract: In a multi-tasking computing system environment, one program is halted and context switched out so that a processor may context switch in a subsequent program for execution. Processor state information exists which reflects the state of the program being context switched out. Storage of this processor state information permits successful resumption of the context switched out program. When the context switched out program is subsequently context switched in, the stored processor information is loaded in preparation for successfully resuming the program at the point in which execution was previously halted. Although, large areas of memory can be allocated to processor state information storage, only a portion of this may need to be preserved across a context switch for successfully saving and resuming the context switched out program.

Abstract: A parallel multiplier for multiplying a multiplicand and multiplier with large bit lengths as well as simultaneously multiplying several multiplicands and multipliers with smaller bit lengths is disclosed. The parallel multiplier receives an N-bit multiplicand operand, an M-bit multiplier operand, and a data length signal. The parallel multiplier calculates an N+M bit product of an N-bit multiplicand from the multiplicand operand and an M-bit multiplier from the multiplier operand when the data length signal selects a first bit length. Furthermore, the parallel multiplier simultaneously calculates an (N+M)/2 bit first product of an N/2 bit first multiplicand from the multiplicand operand and an M/2 bit first multiplier from the multiplier operand, and an (N+M)/2 bit second product of an N/2 bit second multiplicand from the multiplicand operand and an M/2 bit second multiplier from the multiplier operand when the data length signal selects a second bit length.

Abstract: An adder circuit includes various methods to control the carry bit at data boundaries when attempting to process multiple data of multiple types. One method is to generate both propagate and generate signals from the input data and modified propagate and generate signals from the data boundaries, which can then be used in a conventional carry-lookahead adder to produce a resulting sum that is correct regardless of the data type being processed. Another method is to insert special carry blocking, propagating or generating cells at the data boundaries of the input data. These cells are then filled with the appropriate blocking, propagating or generating signals, either by table look-up or circuit implementation using data type and processing type inputs. This data stream can then be added with a conventional adder. However, if the special cell replaces data at the boundaries, another adder can be used to process this boundary data separately prior to inserting the special cell.

Abstract: A cache control unit and a method of controlling a cache. The cache is coupled to a cache accessing device. A first cache request is received from the device. A request identification information is assigned to the first cache request and provided to the requesting device. The first cache request may begin to be processed. A second cache request is received from the cache accessing device. The second cache request is assigned to the first cache request and provided to the requesting device. The first and second cache requests are finally fully serviced.

Abstract: An integrated circuit (IC) device implemented according to an architectural design that specifies that the IC device is required to have one functional module, to perform a first function, connected to another functional module, to perform a second function. The IC device includes a first IC chip having a plurality of first functional modules implemented thereon. Some of the first functional modules are defective and others of the first functional modules are non-defective. At least one of the non-defective first functional modules is operable to perform the first function. The IC device also includes a second IC chip having a plurality of second functional modules implemented thereon. Some of the second functional modules are defective and others of the second functional modules are non-defective. At least one of the non-defective second functional modules is operable to perform the second function.

Abstract: A semiconductor floor plan layout for integrating Data Dependency Comparator (DDC) blocks, Tag Assignment Logic (TAL) blocks, and Register Port Multiplexer (RPM) blocks to conserve valuable semiconductor real estate. The DDC blocks are arranged in rows and columns. The TAL blocks are coupled to the DDC blocks to receive dependency information. The TAL blocks are positioned in one or more of the layout regions so as to be integrated with the DDC blocks to conserve area on the integrated circuit chip. The RPM blocks are coupled to the TAL blocks to receive tag information.

Abstract: A VLSIC page printer controller includes an instruction processor which responds to a host computer and a printer video processor for accessing data from memory under the control of the instruction processor and serializing data for transfer to a printer through a video port. An I/O interface interconnects the printer controller with an I/O bus to which is connected a host computer, memory devices, and other peripheral devices. An internal memory interface connects the printer controller to memory, and the printer video processor is provided with direct memory access (DMA). Data and instruction caches and an instruction ROM are provided on-chip. A RISC instruction processing unit includes as an integral part thereof the special function, circuits of orthogonal rotator, bit/byte mirror, and pixel modification.

Abstract: A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An integer register set includes first (RA[23:0]) and second (RA[31:24]) subsets, and a shadow subset (RT[31:24]). While the data processor is in a first mode, instructions access the first and second subsets. While the data processor is in a second mode, instructions may access the first subset, but any attempts to access the second subset are re-routed to the shadow subset instead, transparently to the instructions, allowing system routines to seemingly use the second subset without having to save and restore data which user routines have written to the second subset. A re-typable register set provides integer width data and floating point width data in response to integer instructions and floating point instructions, respectively.

Abstract: A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a portion of the stream of complex instructions and extracts a first set of instruction bytes starting with the first instruction bytes, using an extract shifter. The set of instruction bytes are then passed to an align latch where they are aligned and output to a next instruction detector. The next instruction detector determines the end of the first instruction based on said set of instruction bytes. An extract shifter is used to extract and provide the next set of instruction bytes to an align shifter which aligns and outputs the next instruction. The process is then repeated for the remaining instruction bytes in the stream of complex instructions.

Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches and stores program instruction sets. Each instruction set includes a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instruction sets and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers which are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instructions in-order.

Abstract: A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accessed by read address ports and for storing instruction operands. A data dependance check circuit is included for determining data dependencies between the instructions. A tag assignment circuit generates one of more tags to specify the location of operands, based on the data dependencies determined by the data dependance check circuit. A set of register file port multiplexers select the tags generated by the tag assignment circuit and pass the tags onto the read address ports of the register file for storing execution results.

Abstract: A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An integer register set includes first (RA[23:0]) and second (RA[31:24]) subsets, and a shadow subset (RT[31:24]). While the data processor is in a first mode, instructions access the first and second subsets. While the data processor is in a second mode, instructions may access the first subset, but any attempts to access the second subset are re-routed to the shadow subset instead, transparently to the instructions, allowing system routines to seemingly use the second subset without having to save and restore data which user routines have written to the second subset. A re-typable register set provides integer width data and floating point width data in response to integer instructions and floating point instructions, respectively.

Abstract: Fast trap mechanism for a microprocessor, wherein a vector trap table is maintained which contains space for a plurality of instructions in each table entry. When a fast trap occurs, control is transferred directly into the table entry corresponding to the trap number. The trap handler can be located completely inside the table entry, or it can transfer control to additional handler code.

Abstract: A method for use in a microprocessor to return execution to a main program after processing an interruption to the sequential processing of instructions from the main instruction stream is disclosed. The method comprises fetching instructions from a main instruction stream to a main buffer section of a prefetch buffer and executing said fetched instructions. The method also provides for handling interruptions to the processing of the main instruction stream and allowing return to the main instruction stream without requiring prefetching of instructions already fetched. Similarly, the method provides for handling interruptions of the processing of interruptions of the processing of the main instruction stream.

Abstract: A semiconductor floorplan layout for integrating a Data Dependency Checker (DDC) circuit and a Tag Assignment Logic (TAL) of a Register Renaming Circuit (RRC) circuit to conserve valuable semiconductor realestate. Floorplans of present invention contemplate laying out the DDC and TAL in such a fashion as to reduce the distance signals must travel between the DDC and TAL, as well as the distance signals must travel between the TAL and RPM. By rearranging selected DDC comparator rows and their associated TAL, a considerable amount of area can be conserved for performing register renaming for up to eight instructions.

Abstract: A memory subsystem including a read-only memory (ROM), a random access read/write memory (RAM) and a selection system for selecting the output of one of the memories for use by downstream circuitry. The selection of the output is based on input address signals so that the contents of the RAM can substitute for the contents of selected locations in the ROM. If a substitution is to be made, an entry is made in a content addressable memory, which stores addresses for which the RAM output is to be substituted for ROM output. A test system is provided to verify the contents of the content addressable memory.