Abstract: Disclosed are a capacitance-to-digital conversion circuit, a capacitance-to-digital conversion method and an electronic chip. The capacitance-to-digital conversion circuit includes a first module, a comparator and an adaptive range-shift module; the first module includes a successive approximation unit, a first adder, a first digital-to-analog converter, a second adder, a third adder and an integrating unit. The first module further includes a second digital-to-analog converter connected to the third adder. The comparator, the adaptive range-shift module and the first adder are connected in series and the comparator is connected to the second digital-to-analog converter. By the present application, the adverse influence caused by the parasitic and interference is well avoided, the capacitance-to-digital conversion circuit may work in a harsh environment, the robustness of the circuit is significantly improved and the application range of the circuit is expanded.

Abstract: Disclosed are compounds of Formula I, methods of using the compounds for inhibiting KRAS activity and pharmaceutical compositions comprising such compounds. The compounds are useful in treating, preventing or ameliorating diseases or disorders associated with KRAS activity such as cancer.

Abstract: Disclosed are a power-aware method, a power-aware system and a converter. The power-aware method includes: receiving an input signal, wherein the input signal is a capacitive type, a resistive type, a voltage type or a current type, coarsely quantizing the input signal and outputting a numerical control code, the numerical control code indicating size information of the input signals, and turning on a corresponding number of power-consuming modules based on the numerical control code. By the power-aware method, the power-aware technical effect of a circuit may be provided and turned-on power-consuming modules always have the most suitable number regardless of the size of the input signals, which may ensure normal operation, and will not waste power consumption due to too many power-consuming modules and energy efficiency is improved as a whole.

Abstract: Disclosed is a capacitive sensor chip based on a power-aware dynamic charge-domain amplifier array. The capacitive sensor chip is based on a zoom architecture and includes: an architecture having two or more stages for capacitive quantization in which a first stage performs coarse quantization using a successive approximation register (SAR) and a second stage performs fine quantization using a delta-sigma modulator, an amplifier in the capacitive sensor chip is powered by a floating capacitor, the floating capacitor is connected to a power supply to being charged and connected to the amplifier to power the amplifier by controlling switches; a first-order integrator of the delta-sigma modulator includes an amplifier array having a scale of N bits and 2N amplifiers where N is a positive integer.

Abstract: An electroosmotic drive module comprises: a porous dielectric film; two electrodes respectively provided on opposite sides of the porous dielectric film; and a porous insulating layer, one electrode being disposed between the porous dielectric film and the insulating layer. An implantable electroosmotic micropump comprises a housing, and at least one electroosmotic drive module is provided in the housing. There are a plurality of electroosmotic drive modules, and the plurality of electroosmotic drive modules are connected in series end to end, such that heterogeneous integrated assembly between different materials such as electrodes, films, and housings can be achieved.

Abstract: A connection structure of a thin film electrode and a housing includes at least one thin film electrode unit and a housing; the electrode unit includes a porous thin film, a first electrode and a second electrode attached to two sides of the film; a part of the film and a part of the first electrode form a first electrical connection unit; a part of the film and a part of the second electrode form a second electrical connection unit; at least one installation groove is provided on the inner wall surface of the housing; the electrode unit is provided in the installation groove; at least one communication unit communicated with the installation groove is further provided on the outer wall surface of the housing; the first electrical connection unit and the second electrical connection unit are respectively communicated with an external circuit of the housing through the communication unit.

Abstract: A self-aligning preparation method for a drain underlap region in a tunnel field effect transistor: designing asymmetric side wall structures on two sides of the gate of a tunnel field effect transistor, the side of the gate closest to the source region being a thin side wall and the side of the gate closest to the drain region being a thick side wall; and using the source region thin side wall as a hard mask for implantation of the source region of the transistor and the drain region thick side wall as a hard mask for implantation of the drain region of the transistor. The present method effectively uses the thin side walls and thick side walls existing in standard CMOS processes to suppress the ambipolar effect of the tunnel field effect transistor without introducing special materials and special processes, and also optimizes the device variation characteristics.

Abstract: Disclosed in the present application are a logic circuit design method and apparatus, and a storage medium. The method comprises: designing and generating an initial MOSFET-TFET hybrid logic circuit, the MOSFET-TFET hybrid logic circuit comprising several logic gates; in the series branch of the initial MOSFET-TFET hybrid logic circuit, replacing a first type of TFET with a MOSFET; the first type of TFET being directly grounded or connected to a power supply and not directly connected to the output ends of the logic gates. The logic circuit design method of the present application overcomes the defect of excessive current attenuation caused by the TFET in the series branch by replacing the first type of TFET in the series branch of the initial logic circuit with a MOSFET The first type of TFET is a TFET that is directly grounded or connected to a power supply and not directly connected to the output ends of the logic gates.

Abstract: Disclosed are a capacitance-to-digital conversion circuit, a capacitance-to-digital conversion method and an electronic chip. The capacitance-to-digital conversion circuit includes a first module, a comparator and an adaptive range-shift module; the first module includes a successive approximation unit, a first adder, a first digital-to-analog converter, a second adder, a third adder and an integrating unit. The first module further includes a second digital-to-analog converter connected to the third adder. The comparator, the adaptive range-shift module and the first adder are connected in series and the comparator is connected to the second digital-to-analog converter. By the present application, the adverse influence caused by the parasitic and interference is well avoided, the capacitance-to-digital conversion circuit may work in a harsh environment, the robustness of the circuit is significantly improved and the application range of the circuit is expanded.

Abstract: Disclosed are a power-aware method, a power-aware system and a converter. The power-aware method includes: receiving an input signal, wherein the input signal is a capacitive type, a resistive type, a voltage type or a current type, coarsely quantizing the input signal and outputting a numerical control code, the numerical control code indicating size information of the input signals, and turning on a corresponding number of power-consuming modules based on the numerical control code. By the power-aware method, the power-aware technical effect of a circuit may be provided and turned-on power-consuming modules always have the most suitable number regardless of the size of the input signals, which may ensure normal operation, and will not waste power consumption due to too many power-consuming modules and energy efficiency is improved as a whole.

Abstract: Disclosed is a capacitive sensor chip based on a power-aware dynamic charge-domain amplifier array. The capacitive sensor chip is based on a zoom architecture and includes: an architecture having two or more stages for capacitive quantization in which a first stage performs coarse quantization using a successive approximation register (SAR) and a second stage performs fine quantization using a delta-sigma modulator, an amplifier in the capacitive sensor chip is powered by a floating capacitor, the floating capacitor is connected to a power supply to being charged and connected to the amplifier to power the amplifier by controlling switches; a first-order integrator of the delta-sigma modulator includes an amplifier array having a scale of N bits and 2N amplifiers where N is a positive integer.

Abstract: The present application discloses a circuit for extracting a feature, a network and a signal processing system. The circuit includes: one or more instant range of change feature extracting units, which are connected in parallel and configured to extract and classify an instant range of change (IROC) feature from an input of an asynchronous pulse coding in the time domain, the input of the asynchronous pulse coding is a pulse request signal and a pulse direction signal obtained by performing time-domain quantization and coding on an analog signal. By the circuit for extracting a feature according to the present application, the instant range of change of an analog input of the asynchronous pulse coding can be directly extracted and classified in the time domain, converting from the time domain to the frequency domain required by the traditional feature extraction process is avoided, and the power consumption overhead is reduced.

Abstract: The present invention relates to the technical field of microfluidics, and specifically relates to an electroosmotic micropump apparatus and an electroosmotic micropump apparatus group. The electroosmotic micropump apparatus in the present invention comprises fluid micro channels and a microneedle electrode; each fluid micro channel is used for communicating a micro flow channel inlet with a micro flow channel outlet for pumping a fluid; the microneedle electrode comprises a first microneedle type electrode and a second microneedle type electrode that are respectively provided at the micro flow channel inlet and the micro flow channel outlet; the first microneedle type electrode and the second microneedle type electrode are oppositely arranged; moreover, neither of the first microneedle type electrode and the second microneedle type electrode is in conduction with the fluid micro channel.

Abstract: A CMOS-MEMS humidity sensor, comprising: a complementary metal oxide semiconductor (CMOS) ASIC readout circuit and a microelectromechanical system (MEMS) humidity sensor. The MEMS humidity sensor is provided on the ASIC readout circuit. The ASIC readout circuit comprises: a substrate, a heating resistor layer, a metal layer, and dielectric layers, the heating resistor layer being located above the substrate, the metal layer being located above the heating resistor layer, and the substrate, the heating resistor layer, and the metal layer being partitioned by dielectric layers. The MEMS humidity sensor comprises: an aluminum electrode layer, a passivation layer, and a humidity sensitive layer, the passivation layer being located above the aluminum electrode layer, and the humidity sensitive layer being located above the passivation layer.

Abstract: A directional coupler is disclosed integrated on a single chip and an integrated circuit based on a standard CMOS process and relates to a field of radio frequency communication. In exemplary implementations, by using a standard CMOS process technology, the directional coupler integrated by a CMOS process is formed by a coil wound by a upper layer of metal lines, a coil wound by a lower layer of metal lines, two tuning capacitor array, and a matching resistor. Two terminals of the coil are a direct terminal and an input terminal; two terminals of the coil are a coupled terminal and an isolation terminal; the terminals of the coils and are intersected at 90°; the coil is wound by an upper metal layer and the coil is wound by a lower metal layer. Further, the insertion loss is low and the isolation degree is large.

Abstract: A directional coupler is disclosed integrated on a single chip and an integrated circuit based on a standard CMOS process and relates to a field of radio frequency communication. In exemplary implementations, by using a standard CMOS process technology, the directional coupler integrated by a CMOS process is formed by a coil winded by a upper layer of metal lines, a coil winded by a lower layer of metal lines, two tuning capacitor array, and a matching resistor. Two terminals of the coil are a direct terminal and an input terminal; two terminals of the coil are a coupled terminal and an isolation terminal; the terminals of the coils and are intersected at 90°; the coil is winded by an upper metal layer and the coil is winded by a lower metal layer. Further, the insertion loss is low and the isolation degree is large.