Abstract: An image processing method is configured to split a deconvolution kernel according to a preset splitting mode to obtain a sub-convolution kernel. And then, determining an original sub-matrix corresponding to the sub-convolution kernel, according to parameters of the sub-convolution kernel and an image feature matrix, and performing a convolution operation on the original sub-matrix corresponding to the sub-convolution kernel by using the sub-convolution kernel to obtain a deconvolution sub-matrix corresponding to each sub-convolution kernel; determining a target feature matrix according to the deconvolution sub-matrix corresponding to the sub-convolution kernel.

Abstract: An image processing method is configured to split a deconvolution kernel according to a preset splitting mode to obtain a sub-convolution kernel. And then, determining an original sub-matrix corresponding to the sub-convolution kernel, according to parameters of the sub-convolution kernel and an image feature matrix, and performing a convolution operation on the original sub-matrix corresponding to the sub-convolution kernel by using the sub-convolution kernel to obtain a deconvolution sub-matrix corresponding to each sub-convolution kernel; determining a target feature matrix according to the deconvolution sub-matrix corresponding to the sub-convolution kernel.

Abstract: A neural network chip and a related product are provided. The neural network chip (103) includes: a memory (102), a data reading/writing circuit, a convolution calculation circuit, wherein the memory is used for storing a feature map; the data reading/writing circuit is used for reading the feature map from the memory and execute an expansion and zero-padding operation on the feature according to configuration information of the feature map, and sending to the convolution calculation circuit (S401); and the convolution calculation circuit is used for performing convolution calculation on the data obtained after the expansion and zero-padding operation to implement a de-convolution operation (S402). The technical solution has advantages of saving memory usage and bandwidth.

Abstract: A neural network chip and a related product are provided. The neural network chip (103) includes: a memory (102), a data reading/writing circuit, a convolution calculation circuit, wherein the memory is used for storing a feature map; the data reading/writing circuit is used for reading the feature map from the memory and execute an expansion and zero-padding operation on the feature according to configuration information of the feature map, and sending to the convolution calculation circuit (S401); and the convolution calculation circuit is used for performing convolution calculation on the data obtained after the expansion and zero-padding operation to implement a de-convolution operation (S402). The technical solution has advantages of saving memory usage and bandwidth.

Abstract: Provided are a data transmission method for a neural network, and a related product. The method includes the following steps: acquiring a weight specification of weight data stored in a memory, comparing the weight specification with a specification of a write memory in terms of size and determining a comparison result; according to the comparison result, dividing the write memory into a first-in first-out write memory and a multiplexing write memory; according to the comparison result, determining data reading policies of the first-in first-out write memory and the multiplexing write memory; and according to the data reading policies, reading weights from the first-in first-out write memory and the multiplexing write memory and loading the weights to a calculation circuit. The technical solution provided by the present application has the advantages of low power consumption and short calculation time.

Abstract: A calculation method includes: receiving a calculation instruction of a parse neural network, obtaining a weight CO*CI*n*m corresponding to the calculation instruction according to the calculation instruction; determining a KERNEL SIZE of the weight, scanning the weight with the KERNEL SIZE as a basic granularity to obtain a weight identifier, storing KERNEL corresponding to a second feature value of the weight identifier, deleting KERNEL corresponding to a first feature value of the weight identifier; scanning all values of the weight identifier; if the value is equal to a second specific value, extracting KERNEL and input data corresponding to the value, performing computation of the input data and the KERNEL to obtain an initial result; if the value is equal to the first feature value, not reading KERNEL and input data corresponding to the value; performing computation of all the initial results to obtain a calculation result of the calculation instruction.

Abstract: Provided are a data transmission method for a neural network, and a related product. The method includes the following steps: acquiring a weight specification of weight data stored in a memory, comparing the weight specification with a specification of a write memory in terms of size and determining a comparison result; according to the comparison result, dividing the write memory into a first-in first-out write memory and a multiplexing write memory; according to the comparison result, determining data reading policies of the first-in first-out write memory and the multiplexing write memory; and according to the data reading policies, reading weights from the first-in first-out write memory and the multiplexing write memory and loading the weights to a calculation circuit. The technical solution provided by the present application has the advantages of low power consumption and short calculation time.

Abstract: The disclosure provides a device for implementing address buffer management of a processor, including: an assembler configured to perform operations to obtain intermediate values when the assembler encodes a set instruction for an address automatic-increment value and boundary values, and to encapsulate the intermediate values into the set instruction for the address automatic-increment value and boundary values; and a processor configured to determine, according to the intermediate values, whether to perform the address automatic-increment operation or the address automatic-decrement operation, so as to achieve the address buffer management.

Abstract: A system and methods are discussed for providing additional capabilities to some instructions associated with loop execution. A standard set of instructions is processed using only a standard instruction size. Some loop instructions are processed with a standard instruction portion of the standard instruction size and an augmented instruction portion. The augmented instruction portion provides additional capabilities associated with the standard instruction portion. The augmented instruction portion can provide capabilities associated with conditional execution of the standard instruction portion or other instructions within a program loop. Furthermore, the augmented instruction portion can provide an additional operand to be used with the standard instruction portion.

Abstract: Information is processed in a data processing system having a branch target buffer (BTB). In one form, an instruction is received and decoded. A determination is made whether the instruction is a taken branch instruction based on a condition code value set by one of a logical operation, an arithmetic operation or a comparison result of the execution of another instruction or execution of the instruction. An instruction specifier associated with the taken branch instruction is used to determine whether to allocate an entry of the branch target buffer for storing a branch target of the taken branch instruction. In one form the instruction specifier is a field of the instruction. Depending upon the value of the branch target buffer allocation specifier, the instruction fetch unit will not allocate an entry in the branch target buffer for unconditional branch instructions.

Abstract: A method of profiling each of a plurality of branch instructions to determine when allocation of an entry in a branch target buffer should occur if the branch is taken. Various factors are used in the determination. In one form, each of the plurality of branch instructions is analyzed to determine a count value of how many times a branch instruction, when executed, is taken during a timeframe. Based upon said analyzing, an instruction field within each of the plurality of branch instructions is set to a value that controls whether allocation of an entry of a branch target buffer should occur when such branch instruction is taken. Other factors, such as determining how long each branch instruction will likely remain in the branch target buffer prior to being replaced, may be used.

Abstract: In one embodiment, a data processing system (10) includes a first master, storage circuitry (35) coupled to the first master (12) for use by the first master (12), a first control storage circuit (38) which stores a first prefetch limit (60), a prefetch buffer (42), and prefetch circuitry (40) coupled to the first control storage circuit, to the prefetch buffer, and to the storage circuitry. In one embodiment, the prefetch circuitry (40) selectively prefetches a predetermined number of lines from the storage circuitry into the prefetch buffer (42) based on whether or not a prefetch counter, initially set to a value indicated by the first prefetch limit, has expired. In one embodiment, the first prefetch limit may therefore be used to control how many prefetches occur between misses in the prefetch buffer.

Abstract: A method for processing scalar and vector executions, where vector executions may be “true” vector operations, CVA, or pseudo-vector operations, PVA. All three types of executions are processed using one architecture. In one embodiment, a compiler analyzes code to identify sections that are vectorizable, and applies either CVA, PVA, or a combination of the two to process these sections. Register overlay is provided for storing load address information and data in PVA mode. Within each CVA and PVA instruction, enable bits describe the data streaming function of the operation. A temporary memory, TM, accommodates variable size vectors, and is used in vector operations, similar to a vector register, to store temporary vectors.

Abstract: Embodiments of the present invention relate generally to data processing systems having instruction folding and methods for controlling execution of a program loop. One embodiment includes detecting execution of a program loop and prefetching data in response to detecting execution of the program loop. Another embodiment includes detecting execution of a program loop and scanning the program loop for remote independent instructions or data dependencies during at least one iteration. Another embodiment includes detecting execution of a program loop and storing intra-loop data dependency information in a dependency bit vector, and using the dependency bit vector to select at least one local independent instruction available for folding. One embodiment includes an instruction folding unit comprising a first controller, a second controller, and a storage unit coupled to the second controller.

Abstract: A system and methods are discussed for providing additional capabilities to some instructions associated with loop execution. A standard set of instructions is processed using only a standard instruction size. Some loop instructions are processed with a standard instruction portion of the standard instruction size and an augmented instruction portion. The augmented instruction portion provides additional capabilities associated with the standard instruction portion. The augmented instruction portion can provide capabilities associated with conditional execution of the standard instruction portion or other instructions within a program loop. Furthermore, the augmented instruction portion can provide an additional operand to be used with the standard instruction portion.

Abstract: A specific implementation is disclosed where a backward branch address instruction is fetched at a branch address. The backward branch instruction has an offset value to define the size of a program loop. A counter is set to a value that is proportional to the size of the loop. In one example the counter is set to the offset value. As each instruction of the loop is executed the counter is modified to indicate a remaining number of instructions in the loop. When no instructions remain in the current pass of the loop, the counter is reset to the offset value and the loop is repeated until a termination condition encountered. As part of the implementation the instruction after the branch instruction is read and stored prior to the loop being executed.

Abstract: A loop cache (26) is used in a data processing system for supplying instructions to a CPU to avoid accessing a main memory. Whether instructions stored in the loop cache can be supplied to the CPU is determined by a distributed TAG associated with the instruction address computed by the CPU. The instruction address includes an LCACHE index portion (42), an ITAG portion (44), and a GTAG (46). LCACHE index (42) selects corresponding locations in each of an ITAG array (50), an instruction array (52), and a valid bit array (54). A stored GTAG value (48) is chosen irrespective of where LCACHE index (42) is pointing. The GTAG portion of the instruction address (40) is compared to the stored GTAG value (48). The ITAG portion (44) of instruction address (40) is compared with the indexed ITAG of the ITAG array (50). If both the GTAG and ITAG compare favorably, the instruction is supplied from the loop cache to the CPU, rather than from main memory.

Abstract: A data processing system (20) has a cache (26) that does not use a TAG array for storing a TAG address as in a conventional cache. The cache (26), according to one embodiment, uses a state machine (30) for transitioning the cache (26) to an active state in response to a change of flow instruction which is a short backward branch instruction of a predetermined displacement. The predetermined displacement is less than the number of entries in the cache (26), so the cache can remain active as long as the program is in a loop which can be contained entirely within the cache. A look ahead feature for the valid bit array is provided that associates the valid bit for a current instruction with a previous instruction, such that during a read of the cache, the valid bit for a next instruction is checked with the same index used to read the current instruction.