Patents by Inventor Lea-Teng Lee

Lea-Teng Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9974181
    Abstract: A module includes a printed circuit board (PCB) having a substrate, component pads on a top surface of the substrate, and contact pads formed on a bottom surface of the substrate. The module further includes a mold compound disposed over the PCB; an external shield disposed over a top surface of the mold compound and on side surfaces of the mold compound and the PCB, where the external shield is configured to provide shielding of at least one component connected to at least one component pad from electromagnetic radiation; and a back-spill barrier formed on the bottom of the substrate. The back-spill barrier surrounds the contact pads, and is configured to prevent the external shield from making contact with the contact pads.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: May 15, 2018
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Sarah Haney, Deog Soon Choi, Hyun Mo Ku, Lea-Teng Lee, Nitesh Kumbhat, Ah Ron Lee
  • Patent number: 9865479
    Abstract: A method is provided for attaching components to pads on a PCB, where total accumulated tolerances are reduced by separating accumulated tolerances into multiple processes. The method includes performing first and second processes having first and second accumulated tolerances, respectively. The first process includes placing a first stencil over the PCB, the first stencil defining first apertures corresponding to the pads; printing solder paste onto the pads using the first stencil; and reflowing the printed solder paste to form corresponding solder bumps on the pads. The second process includes placing a second stencil over the PCB, the second stencil defining second apertures corresponding to the pads; printing flux onto the solder bumps using the second stencil; placing at least one component on the printed flux; and reflowing the printed flux and the solder bumps to form corresponding solder joints between the at least one component and the first pads, respectively.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: January 9, 2018
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Wei-Shun Wang, Li Sun, Ashish Alawani, Lea-Teng Lee
  • Publication number: 20170301559
    Abstract: A method is provided for attaching components to pads on a PCB, where total accumulated tolerances are reduced by separating accumulated tolerances into multiple processes. The method includes performing first and second processes having first and second accumulated tolerances, respectively. The first process includes placing a first stencil over the PCB, the first stencil defining first apertures corresponding to the pads; printing solder paste onto the pads using the first stencil; and reflowing the printed solder paste to form corresponding solder bumps on the pads. The second process includes placing a second stencil over the PCB, the second stencil defining second apertures corresponding to the pads; printing flux onto the solder bumps using the second stencil; placing at least one component on the printed flux; and reflowing the printed flux and the solder bumps to form corresponding solder joints between the at least one component and the first pads, respectively.
    Type: Application
    Filed: April 15, 2016
    Publication date: October 19, 2017
    Inventors: Wei-Shun Wang, Li Sun, Ashish Alawani, Lea-Teng Lee
  • Publication number: 20170280561
    Abstract: A module includes a printed circuit board (PCB) having a substrate, component pads on a top surface of the substrate, and contact pads formed on a bottom surface of the substrate. The module further includes a mold compound disposed over the PCB; an external shield disposed over a top surface of the mold compound and on side surfaces of the mold compound and the PCB, where the external shield is configured to provide shielding of at least one component connected to at least one component pad from electromagnetic radiation; and a back-spill barrier formed on the bottom of the substrate. The back-spill barrier surrounds the contact pads, and is configured to prevent the external shield from making contact with the contact pads.
    Type: Application
    Filed: March 24, 2016
    Publication date: September 28, 2017
    Inventors: Sarah Haney, Deog Soon Choi, Hyun Mo Ku, Lea-Teng Lee, Nitesh Kumbhat, Ah Ron Lee
  • Publication number: 20170215278
    Abstract: A coreless substrate of a printed circuit board is provided. The coreless substrate includes a first outer metal layer; a first primer layer formed on the first outer metal layer; a first layer of functional prepreg material formed on the first primer layer; a second primer layer formed over the first layer of functional prepreg material; and a second outer metal layer formed on the second primer layer. The first outer metal layer corresponds to a first outer most surface of the printed circuit board, and the second outer metal layer corresponds to a second outer most surface of the printed circuit board.
    Type: Application
    Filed: January 27, 2016
    Publication date: July 27, 2017
    Inventors: Padam Jain, Sarah Haney, Lea-Teng Lee
  • Patent number: 9668340
    Abstract: A build-up process for fabricating a multi-layer PCB is provided that prevents, or at least reduces the lengths of, overhangs in the finishing metal layer that is plated onto the electrical contact metal layer. The metal seed layer is etched away prior to plating the finishing metal layer onto the electrical contact metal layer. The electrical contact metal layer is covered with a layer of dielectric material, which is then patterned to selectively expose preselected areas of the electrical contact metal layer. The exposed preselected areas of the electrical contact metal layer are then plated with the finishing layer of metal. The result is that overhangs are eliminated or at least greatly reduced in length. In addition, the dielectric material layer serves a function similar to that of a solder mask and obviates the need to apply the oxide to serve as a solder mask.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: May 30, 2017
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Jack Ajoian, Lea-Teng Lee
  • Publication number: 20170018501
    Abstract: An apparatus, a semiconductor package including the apparatus and a method are disclosed. The apparatus includes a substrate, pluralities of vias disposed in the substrate. The vias are disposed in a hexagonal arrangement.
    Type: Application
    Filed: October 31, 2015
    Publication date: January 19, 2017
    Inventors: Marshall Maple, Ashish Alawani, Li Sun, Sarah Haney, Lea-Teng Lee, Wei Yao
  • Publication number: 20150351229
    Abstract: A printed circuit board (PCB) comprises a non-conductive base layer, a conductive interconnect disposed on the non-conductive base layer and comprising at least two surface pads separated by a trench, and a insulating dam disposed in the trench, wherein the insulating dam electrically isolates the at least two surface pads and has an upper surface that is substantially co-planar with respective upper surfaces of the at least two surface pads.
    Type: Application
    Filed: May 28, 2014
    Publication date: December 3, 2015
    Applicant: Avago Technologies General IP (Singapore) Pte. Ltd
    Inventors: Lea-Teng Lee, Sarah Haney