Patents by Inventor Leah Marie P. Pastel

Leah Marie P. Pastel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and structure for defect monitoring of semiconductor devices using power bus wiring grids
    Patent number: 7285860
    Abstract: A method for implementing defect inspection of an integrated circuit includes configuring a power bus grid structure on a first metal interconnect level, the power bus grid structure including a first plurality of wire pairs. The first plurality of wire pairs is arranged in a manner such that a first wire in each of the first plurality of wire pairs is electrically coupled to conductive structures beneath the first metal interconnect level, and a second wire in each of the first plurality of wire pairs is initially electrically isolated from the conductive structures beneath the first metal interconnect level. The first wire in each of the first plurality of wire pairs is biased to a known voltage, and a charge contrast inspection is performed between the first wire and the second wire of each of the first plurality of wire pairs.
    Type: Grant
    Filed: March 28, 2006
    Date of Patent: October 23, 2007
    Assignee: International Business Machines Corporation
    Inventors: John M. Cohn, Leah Marie P. Pastel, Thomas G. Sopchak, David P. Vallett
  • Method and structure for defect monitoring of semiconductor devices using power bus wiring grids
    Patent number: 7078248
    Abstract: A method for implementing defect inspection of an integrated circuit includes configuring a power bus grid structure on a first metal interconnect level, the power bus grid structure including a first plurality of wire pairs. The first plurality of wire pairs is arranged in a manner such that a first wire in each of the first plurality of wire pairs is electrically coupled to conductive structures beneath the first metal interconnect level, and a second wire in each of the first plurality of wire pairs is initially electrically isolated from the conductive structures beneath the first metal interconnect level. The first wire in each of the first plurality of wire pairs is biased to a known voltage, and a charge contrast inspection is performed between the first wire and the second wire of each of the first plurality of wire pairs.
    Type: Grant
    Filed: June 18, 2004
    Date of Patent: July 18, 2006
    Assignee: International Business machines Corporation
    Inventors: John M. Cohn, Leah Marie P. Pastel, Thomas G. Sopchak, David P. Vallett