Patents by Inventor Leah Marie Pfeifer Pastel
Leah Marie Pfeifer Pastel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10024914Abstract: A method and system of testing an integrated circuit (IC), using a multiple input shift register (MISR) with supporting hardware for diagnosing failure locations in an IC with built-in self-test (BIST) logic, including an On-Product MISR. The system includes BIST logic of a circuit under test (CUT) and a tester including an isolation hash table (IHT) that translates signature fail data of the MISR to a failure location of a latch in the CUT. Signature fail data, and consequently, failure locations in the CUT, are obtained by standard testing of the CUT, testing of selected single channels of the CUT, and data insertion functions to the selected single channels of the CUT to obtain compressed MISR signature changes that, when translated, provide failure locations in the CUT.Type: GrantFiled: June 29, 2016Date of Patent: July 17, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Steven M. Douskey, Amanda R. Kaufer, Leah Marie Pfeifer Pastel
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Publication number: 20180003768Abstract: A method and system of testing an integrated circuit (IC), using a multiple input shift register (MISR) with supporting hardware for diagnosing failure locations in an IC with built-in self-test (BIST) logic, including an On-Product MISR. The system includes BIST logic of a circuit under test (CUT) and a tester including an isolation hatch table (IHT) that translates signature fail data of the MISR to a failure location of a latch in the CUT. Signature fail data, and consequently, failure locations in the CUT, are obtained by standard testing of the CUT, testing of selected single channels of the CUT, and data insertion functions to the selected single channels of the CUT to obtain compressed MISR signature changes that, when translated, provide failure locations in the CUT.Type: ApplicationFiled: June 29, 2016Publication date: January 4, 2018Applicant: GLOBALFOUNDRIES INC.Inventors: STEVEN M. DOUSKEY, AMANDA R. KAUFER, LEAH MARIE PFEIFER PASTEL
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Patent number: 8136082Abstract: A method of testing an integrated circuit. The method includes selecting a set of physical features of nets and devices of the integrated circuit, the integrated circuit having pattern input points and pattern observation points connected by the nets, each of the nets defined by an input point and all fan out paths to (i) input points of other nets of the nets or (ii) to the pattern observation points; selecting a measurement unit for each feature of the set of features; assigning a weight to each segment of each fan out path based on a number of the measurement units of the feature in each segment of each fan out path of each of the nets; and generating a set of test patterns optimized for test-coverage and cost based on the weights assigned to each segment of each of the nets of the integrated circuit.Type: GrantFiled: May 6, 2011Date of Patent: March 13, 2012Assignee: International Business Machines CorporationInventors: Rao H. Desineni, Maroun Kassab, Franco Motika, Leah Marie Pfeifer Pastel
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Publication number: 20110214102Abstract: A method of testing an integrated circuit. The method includes selecting a set of physical features of nets and devices of the integrated circuit, the integrated circuit having pattern input points and pattern observation points connected by the nets, each of the nets defined by an input point and all fan out paths to (i) input points of other nets of the nets or (ii) to the pattern observation points; selecting a measurement unit for each feature of the set of features; assigning a weight to each segment of each fan out path based on a number of the measurement units of the feature in each segment of each fan out path of each of the nets; and generating a set of test patterns optimized for test-coverage and cost based on the weights assigned to each segment of each of the nets of the integrated circuit.Type: ApplicationFiled: May 6, 2011Publication date: September 1, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Rao H. Desineni, Maroun Kassab, Franco Motika, Leah Marie Pfeifer Pastel
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Patent number: 7971176Abstract: A method of testing an integrated circuit. The method includes selecting a set of physical features of nets and devices of the integrated circuit, the integrated circuit having pattern input points and pattern observation points connected by the nets, each of the nets defined by an input point and all fan out paths to (i) input points of other nets of the nets or (ii) to the pattern observation points; selecting a measurement unit for each feature of the set of features; assigning a weight to each segment of each fan out path based on a number of the measurement units of the feature in each segment of each fan out path of each of the nets; and generating a set of test patterns optimized for test-coverage and cost based on the weights assigned to each segment of each of the nets of the integrated circuit.Type: GrantFiled: March 18, 2008Date of Patent: June 28, 2011Assignee: International Business Machines CorporationInventors: Rao H. Desineni, Maroun Kassab, Franco Motika, Leah Marie Pfeifer Pastel
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Patent number: 7898045Abstract: Acceleration and voltage measurement devices and methods of fabricating acceleration and voltage measurement devices. The acceleration and voltage measurement devices including an electrically conductive plate on a top surface of a first insulating layer; a second insulating layer on a top surface of the conductive plate, the top surface of the plate exposed in an opening in the second insulating layer; conductive nanotubes suspended across the opening, and electrically conductive contacts to the nanotubes.Type: GrantFiled: July 2, 2008Date of Patent: March 1, 2011Assignee: International Business Machines CorporationInventors: Toshiharu Furukawa, Mark Charles Hakey, Steven John Holmes, David Vaclav Horak, Charles William Koburger, III, Leah Marie Pfeifer Pastel
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Patent number: 7870519Abstract: A method for testing an integrated circuit and analyzing test data. The method includes: defining a set of signal path selection criteria; selecting a subset of signal paths of an integrated circuit design, the selecting signal paths meeting the selection criteria; identifying pattern observation points for each signal path of the subset of signal paths; selecting a set of features associated with the integrated circuit design; applying a set of test patterns to one or more integrated circuit chips; determining failing signal paths of the subset of signal paths for each integrated circuit chip; mapping failing signal paths of the subset of signal paths to the set of features to generate a correspondence between the failing signal paths and the features; and analyzing the correspondence and identifying suspect features of the set of features based on the analyzing.Type: GrantFiled: November 19, 2007Date of Patent: January 11, 2011Assignee: International Business Machines CorporationInventors: Rao H. Desineni, Maroun Kassab, Leah Marie Pfeifer Pastel
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Patent number: 7629192Abstract: Acceleration and voltage measurement devices and methods of fabricating acceleration and voltage measurement devices. The acceleration and voltage measurement devices including an electrically conductive plate on a top surface of a first insulating layer; a second insulating layer on a top surface of the conductive plate, the top surface of the plate exposed in an opening in the second insulating layer; conductive nanotubes suspended across the opening, and electrically conductive contacts to the nanotubes.Type: GrantFiled: October 13, 2005Date of Patent: December 8, 2009Assignee: International Business Machines CorporationInventors: Toshiharu Furukawa, Mark Charles Hakey, Steven John Holmes, David Vaclav Horak, Charles William Koburger, III, Leah Marie Pfeifer Pastel
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Publication number: 20090240458Abstract: A method of testing an integrated circuit. The method includes selecting a set of physical features of nets and devices of the integrated circuit, the integrated circuit having pattern input points and pattern observation points connected by the nets, each of the nets defined by an input point and all fan out paths to (i) input points of other nets of the nets or (ii) to the pattern observation points; selecting a measurement unit for each feature of the set of features; assigning a weight to each segment of each fan out path based on a number of the measurement units of the feature in each segment of each fan out path of each of the nets; and generating a set of test patterns optimized for test-coverage and cost based on the weights assigned to each segment of each of the nets of the integrated circuit.Type: ApplicationFiled: March 18, 2008Publication date: September 24, 2009Inventors: Rao H. Desineni, Maroun Kassab, Franco Motika, Leah Marie Pfeifer Pastel
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Publication number: 20090132976Abstract: A method for testing an integrated circuit and analyzing test data. The method includes: defining a set of signal path selection criteria; selecting a subset of signal paths of an integrated circuit design, the selecting signal paths meeting the selection criteria; identifying pattern observation points for each signal path of the subset of signal paths; selecting a set of features associated with the integrated circuit design; applying a set of test patterns to one or more integrated circuit chips; determining failing signal paths of the subset of signal paths for each integrated circuit chip; mapping failing signal paths of the subset of signal paths to the set of features to generate a correspondence between the failing signal paths and the features; and analyzing the correspondence and identifying suspect features of the set of features based on the analyzing.Type: ApplicationFiled: November 19, 2007Publication date: May 21, 2009Inventors: Rao H. Desineni, Maroun Kassab, Leah Marie Pfeifer Pastel
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Publication number: 20080258246Abstract: Acceleration and voltage measurement devices and methods of fabricating acceleration and voltage measurement devices. The acceleration and voltage measurement devices including an electrically conductive plate on a top surface of a first insulating layer; a second insulating layer on a top surface of the conductive plate, the top surface of the plate exposed in an opening in the second insulating layer; conductive nanotubes suspended across the opening, and electrically conductive contacts to said nanotubes.Type: ApplicationFiled: July 2, 2008Publication date: October 23, 2008Inventors: Toshiharu Furukawa, Mark Charles Hakey, Steven John Holmes, David Vaclav Horak, Charles William Koburger, Leah Marie Pfeifer Pastel
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Patent number: 7007214Abstract: A method and system for locating connector defects in a defective scan chain that has a parallel non-defective scan chain on a different wiring level, with both scan chains being laid out in a regular array pattern. A predetermined bit sequence is scanned into the defective scan chain. The contents of the defective scan chain are then parallel shifted into the non-defective scan chain. The contents of the non-defective scan chain is then scanned out and compared with the predetermined bit sequence. The comparison of the scanned out bits with the predetermined bit sequence facilitates locating both physically and logically where a connector defect has occurred in the defective scan chain.Type: GrantFiled: June 30, 2003Date of Patent: February 28, 2006Assignee: International Business Machines CorporationInventors: Steven Michael Eustis, Leah Marie Pfeifer Pastel, Thomas Richard Bednar, Thomas Gregory Sopchak, Jeffery Howard Oppold
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Publication number: 20040268195Abstract: A method and system for locating connector defects in a defective scan chain that has a parallel non-defective scan chain on a different wiring level, with both scan chains being laid out in a regular array pattern. A predetermined bit sequence is scanned into the defective scan chain. The contents of the defective scan chain are then parallel shifted into the non-defective scan chain. The contents of the non-defective scan chain is then scanned out and compared with the predetermined bit sequence. The comparison of the scanned out bits with the predetermined bit sequence facilitates locating both physically and logically where a connector defect has occurred in the defective scan chain.Type: ApplicationFiled: June 30, 2003Publication date: December 30, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Steven Michael Eustis, Leah Marie Pfeifer Pastel, Thomas Richard Bednar, Thomas Gregory Sopchak, Jeffery Howard Oppold