Patents by Inventor Leah Miller
Leah Miller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11983320Abstract: An example wearable device that includes a conductive deformable fabric is described herein. The conductive deformable fabric has a conductive trace that has a non-extendable fixed length along a first axis, and the conductive trace is sewn into a fabric structure to produce a conductive deformable material. The fabric structure includes a stitch pattern that facilitates the conductive trace to unfold and fold in an oscillating fashion to allow the conductive trace to expand and contract, respectively, along the first axis without exceeding the fixed length of the conductive trace. The conductive deformable material is positioned within the wearable device such that when the wearable device is worn, the stitch pattern is over a joint of the user to allow the stitch pattern to expand or contract along with the movement of the joint.Type: GrantFiled: February 24, 2023Date of Patent: May 14, 2024Assignee: META PLATFORMS TECHNOLOGIES, LLCInventors: Simge Uzun, Mary Ellen Margaret Berglund, Stuart Wayne Dealey, Simon John Baines, Amy Lynne Stoltzfus, Russell Liam Warila, Phelan Miller, Christopher Bradford Doughty, Leah Resneck, Katherine Cagen, Cameron Elliot Glasscock, Dylan Downey, Anjali Khemani
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Patent number: 7829424Abstract: The present invention is directed to a method of fabricating an integrated circuit package having decoupling capacitors using a package design conceived for use without decoupling capacitors. The package is implemented with a minimal redesign of the original design and not requiring any redesign of the signal trace pattern. The invention involves replacing top and bottom bond pads with via straps and then covering the top and bottom reference planes with a dielectric layer having conductive vias that electrically connect with the underlying via straps. Planes having the opposite polarity of the underlying reference plane are then formed on the dielectric layer. These planes include an array of bonding pads in registry with the vias. Decoupling capacitors are mounted to the top of the package and electrically connected with the plane on top of the package and the immediately underlying reference plane without the electrical connections to the capacitors passing through the signal planes of the package.Type: GrantFiled: July 16, 2008Date of Patent: November 9, 2010Assignee: LSI CorporationInventors: Leah Miller, Ivor Barber, Aritharan Thurairajaratnam
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Semiconductor package having discrete non-active electrical components incorporated into the package
Patent number: 7791210Abstract: Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate having an integrated circuit die attached thereto. The substrate further includes at least one signal layer having a plurality of electrical signal traces formed thereon. The package includes a discrete non-active electrical component mounted on the package so that the integrated circuit die is electrically connected with an electrical signal trace of the package through the discrete non-active electrical component. And in one particular implementation, the discrete non-active electrical component comprises a capacitive element arranged in series between the electrical signal traces and the die so that the capacitor operates as a package mounted AC coupling capacitor.Type: GrantFiled: November 5, 2003Date of Patent: September 7, 2010Assignee: LSI CorporationInventors: Leah Miller, Aritharan Thurairajaratnam -
Patent number: 7508062Abstract: The present invention is directed to a method of fabricating an integrated circuit package having decoupling capacitors using a package design conceived for use without decoupling capacitors. The package is implemented with a minimal redesign of the original design and not requiring any redesign of the signal trace pattern. The invention involves replacing top and bottom bond pads with via straps and then covering the top and bottom reference planes with a dielectric layer having conductive vias that electrically connect with the underlying via straps. Planes having the opposite polarity of the underlying reference plane are then formed on the dielectric layer. These planes include an array of bonding pads in registry with the vias. Decoupling capacitors are mounted to the top of the package and electrically connected with the plane on top of the package and the immediately underlying reference plane without the electrical connections to the capacitors passing through the signal planes of the package.Type: GrantFiled: March 11, 2005Date of Patent: March 24, 2009Assignee: LSI CorporationInventors: Leah Miller, Ivor Barber, Aritharan Thurairajaratnam
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Publication number: 20080272863Abstract: The present invention is directed to a method of fabricating an integrated circuit package having decoupling capacitors using a package design conceived for use without decoupling capacitors. The package is implemented with a minimal redesign of the original design and not requiring any redesign of the signal trace pattern. The invention involves replacing top and bottom bond pads with via straps and then covering the top and bottom reference planes with a dielectric layer having conductive vias that electrically connect with the underlying via straps. Planes having the opposite polarity of the underlying reference plane are then formed on the dielectric layer. These planes include an array of bonding pads in registry with the vias. Decoupling capacitors are mounted to the top of the package and electrically connected with the plane on top of the package and the immediately underlying reference plane without the electrical connections to the capacitors passing through the signal planes of the package.Type: ApplicationFiled: July 16, 2008Publication date: November 6, 2008Applicant: LSI LOGIC CORPORATIONInventors: LEAH MILLER, IVOR BARBER, ARITHARAN THURAIRAJARATNAM
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Patent number: 7267880Abstract: A substrate having a surface carrying a removable transparent film that can be removed by the surface by a desired washing process, and removable presence indicator associated with the removable transparent film, the presence indicator being removable by the same desired washing process as the removable transparent film. A method of producing a substrate having a presence indicator in contact with a removable transparent film a method of washing a substrate having a presence indicator in contact with a removable transparent film are also disclosed.Type: GrantFiled: June 14, 2004Date of Patent: September 11, 2007Assignee: Cardinal CG CompanyInventors: Leah Miller, Annette Krisko, Klaus Hartig, Roger O'Shaughnessy, Gary Pfaff
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Publication number: 20070114644Abstract: A family of package substrates adapted to receive a family of integrated circuits having different sizes and provide electrical connections between the integrated circuits and a circuit board. Each package substrate in the family includes a package substrate having a die side and a circuit board side. The package substrate has a size that is consistent for all of the package substrates in the family of package substrates. The die side has integrated circuit contacts disposed in a pattern designed to make electrical connections to a given integrated circuit in the family of integrated circuits for which the package substrate is designed, as defined by locations of contacts on the given integrated circuit. The circuit board side has circuit board contacts disposed in a pattern and with functional assignments that are consistent for all of the package substrates in the family of package substrates.Type: ApplicationFiled: November 18, 2005Publication date: May 24, 2007Inventors: Leah Miller, Jeffrey Hall
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Publication number: 20070023930Abstract: The embodiments of the present invention are directed toward the design of routing patterns, including elements such as contacts, traces, and vias, for high speed differential signal pairs in integrated circuit package substrates.Type: ApplicationFiled: July 29, 2005Publication date: February 1, 2007Inventors: Leah Miller, Gregory Winn
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Publication number: 20060223341Abstract: A pattern of contacts that includes high speed transmitter contacts disposed in a first portion of the pattern, where the high speed transmitter contacts are disposed in transmitter differential pairs. High speed receiver contacts are disposed in a second portion of the pattern, where the first portion of the pattern is not interspersed with the second portion of the pattern, and the high speed receiver contacts are disposed in receiver differential pairs. At least one unbroken line of other contacts is disposed between the first portion of the pattern and the second portion of the pattern, where the other contacts do not contain any high speed transmitter contacts and high speed receiver contacts. Low speed IO contacts are disposed in a third portion of the pattern, where the third portion of the pattern is disposed in an interior portion of the pattern relative to both the first portion of the pattern and the second portion of the pattern.Type: ApplicationFiled: April 1, 2005Publication date: October 5, 2006Inventors: Arun Ramakrishnan, Farshad Ghahghahi, Aritharan Thurairajaratnam, Leah Miller
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Publication number: 20060202303Abstract: The present invention is directed to a method of fabricating an integrated circuit package having decoupling capacitors using a package design conceived for use without decoupling capacitors. The package is implemented with a minimal redesign of the original design and not requiring any redesign of the signal trace pattern. The invention involves replacing top and bottom bond pads with via straps and then covering the top and bottom reference planes with a dielectric layer having conductive vias that electrically connect with the underlying via straps. Planes having the opposite polarity of the underlying reference plane are then formed on the dielectric layer. These planes include an array of bonding pads in registry with the vias. Decoupling capacitors are mounted to the top of the package and electrically connected with the plane on top of the package and the immediately underlying reference plane without the electrical connections to the capacitors passing through the signal planes of the package.Type: ApplicationFiled: March 11, 2005Publication date: September 14, 2006Inventors: Leah Miller, Ivor Barber, Aritharan Thurairajaratnam
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Publication number: 20050093173Abstract: Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate having an integrated circuit die attached thereto. The substrate further includes at least one signal layer having a plurality of electrical signal traces formed thereon. The package includes a discrete non-active electrical component mounted on the package so that the integrated circuit die is electrically connected with an electrical signal trace of the package through the discrete non-active electrical component. And in one particular implementation, the discrete non-active electrical component comprises a capacitive element arranged in series between the electrical signal traces and the die so that the capacitor operates as a package mounted AC coupling capacitor.Type: ApplicationFiled: November 5, 2003Publication date: May 5, 2005Inventors: Leah Miller, Aritharan Thurairajaratnam
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Publication number: 20040258890Abstract: A substrate having a surface carrying a removable transparent film that can be removed by the surface by a desired washing process, and removable presence indicator associated with the removable transparent film, the presence indicator being removable by the same desired washing process as the removable transparent film. A method of producing a substrate having a presence indicator in contact with a removable transparent film a method of washing a substrate having a presence indicator in contact with a removable transparent film are also disclosed.Type: ApplicationFiled: June 14, 2004Publication date: December 23, 2004Inventors: Leah Miller, Annette Krisko, Klaus Hartig, Roger O'Shaughnessy, Gary Pfaff