Patents by Inventor Leda Villalobos

Leda Villalobos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for determining the location of an alignment mark on a wafer
    Publication number: 20030025517
    Abstract: An alignment technique can be used to align a semiconductor wafer during wafer testing. During a gross alignment process, a bump pattern on the wafer surface is located. Based on a known relative location relationship between the bump pattern and a fiducial on the wafer surface, the fiducial can be located. The wafer can then be initially aligned. During a fine alignment process, the bump pattern technique can again be used and additional alignment performed. Blurring can be used so that features other than bumps become less discernable.
    Type: Application
    Filed: July 11, 2002
    Publication date: February 6, 2003
    Applicant: Electrogas, Inc.
    Inventors: Cary Kiest, Leda Villalobos
  • Method and apparatus for generating values for selected pixels used in evaluating semiconductor wafer bumps
    Publication number: 20020158643
    Abstract: Plural light sources are provided for directing ring patterns of light toward at least one reflective bump formed on and projecting from a first wafer surface of a semiconductor wafer. The intensity of light from the light sources may be varied and may be varied independently of one another. A method and apparatus for adjusting at least one pixel value is also disclosed.
    Type: Application
    Filed: January 11, 2002
    Publication date: October 31, 2002
    Applicant: Electroglas Inc.
    Inventor: Leda Villalobos