Abstract: In a JTAG test and debug environment, the signal groups for boundary scans can have several lengths including signal groups that are longer that the shift register out. A storage unit is provided with a plurality of storage location lengths. The boundary scan signal groups are stored in a location having a suitable storage capacity. The command that transfers the boundary scan signal group includes a parameter identifying the relevant location. The scan control unit, upon receiving the command, transfers the entire boundary scan signal group as a result this command even if several transfers through the shift register out are required.

Abstract: In a test and debug environment using a JTAG protocol to test a target processing unit, apparatus for multi-value polling permits a poll unit, associated with the scan controller, to determine whether one of several possible signal groups is present in the received data stream. The test and debug unit generates a series of numbers, each number corresponding to a preselected signal groups. The corresponding field in the received data stream is decoded to provide a series of output signals, each output signal corresponding to one group. The output signals of the decoder are compared to corresponding numbers of the expected value. When a signal from the decoder unit is found to correspond to one of the selected data number, the poll operation is a success.

Abstract: In a multi processor environment wherein the processors are capable of implementing a streaming data mode of operation, a technique is provided that reduces the number of bits shifted through the scan chain necessary to select a processor for operating in the streaming data mode. All test control device associated with the processor have an instruction entered therein. After execution of the instruction, all of the processors are entered in a bypass mode of operation. Then, a logic “0” in the bypass register will cause the associated target processor to enter the streaming data mode, while a logic “1” in the bypass register will cause the processor to enter the bypass mode. To select a new target processor, logic “1”s in the bypass register will reset the test control unit and thereafter the entry of a logic “1” will cause the non-target processors to enter the bypass mode, while a logic “0” in a bypass register will select the new target processor (i.e., for operating in the streaming data mode).

Abstract: In a JTAG test and debug environment, the parameters that are accessed by command include a delay parameter. The delay parameter prevents the subsequent command from being executed until both the original command has been executed and the clock cycles indicated by the delay parameter have been completed. Because the time delay is included as a parameter identified by the command, the delay parameter can be programmed.

Abstract: A method for debugging a target processor is provided that includes storing a plurality of data values to be sent to the target processor in a first-in first-out (FIFO) buffer unit, saving a copy of an address in a read address counter of the FIFO buffer unit, wherein the address is that of an initial data value of a sequential portion of the plurality of data values, performing a transfer operation to send the sequential portion to the target processor, wherein the read address counter is incremented as each data value is sent. The method also includes resetting the read address counter with the copy of the address if the transfer operation fails and performing the transfer operation again.

Abstract: A reconfigurable cable/pod unit replaces the cable/pod unit coupling an emulation unit and a target processor. The reconfigurable cable/pod unit includes the discrete logic elements, a programmable unit and interface logic. The programmable unit and the interface unit permit the pod unit to assign conductors to the coupled cable. The interface unit includes storage and other logic elements that compensate for the differences in clock speeds and in rates of data exchange between the emulation unit and the target processor. No changes are necessary in the emulation unit to use the reconfigurable cable/pod unit. The reconfigurable cable pod unit permits, by changing the programming in the programmable unit, to operate in selectable modes, to provide a selectable interface to the target processor, to implement changes and upgrades in the testing procedures, and to test different types of target processors.

Abstract: In a test configuration in which an emulator unit is separated from a target processor under test, the effect of the emulator cable (and pod unit) on the distortion of the signals returned from the processor can be determined by a switch in which signals from the emulator unit are applied to conductor in which signals are returned to the emulator unit, the switch being located in the vicinity of the target processor. In certain test environments, addition switches can be provided proximate the target processor to isolate the emulator cable conductor signals from the target processor.

Abstract: In a cable electrically coupling a target processor and an emulator/test unit, two sense lines are selected that have corresponding terminals on the connects that are symmetrical under 180° rotation of the connectors. Characteristics of at least one sense line are determined. Based on the characteristics of at least one of the sense lines, the relative orientation of the sense lines can be determined. With this determination, the terminals to which the sense lines are coupled in the target processor can be determined. Signals can be applied to and/or received from at least one sense line. In the preferred embodiment, the sense line coupled to the /TRST JTAG terminal of the target processor can be identified. The characteristics of at least one sense line can determine the signals associate with each cable conductor.

Abstract: In a multi processor environment wherein the processors are capable of implementing a streaming data mode of operation, a technique is provided that reduces the number of bits shifted through the scan chain necessary to select a processor for operating in the streaming data mode. All test control device associated with the processor have an instruction entered therein. After execution of the instruction, all of the processors are entered in a bypass mode of operation. Then, a logic “0” in the bypass register will cause the associated target processor to enter the streaming data mode, while a logic “1” in the bypass register will cause the processor to enter the bypass mode.

Abstract: A reconfigurable cable/pod unit is adapted to replace the cable/pod unit coupling an emulation unit and a target processor. The original cable/pod unit includes discrete logic elements in the pod unit that provides an interface for exchanging JTAG and related timing and control signals between the emulation unit and the target processor. The reconfigurable cable/pod unit includes the discrete logic elements, a programmable unit and interface logic. The programmable unit and the interface unit permit the pod unit to assign the conductors of the coupled cable. The interface unit includes storage and other logic elements that compensate for differences in clock speeds and in rates of data exchange between the emulation unit and the target processor. No changes are necessary in the emulation unit to use the reconfigurable cable/pod unit.