Abstract: A salt spray resistant structure of fan motor assembly includes a silicon steel sheet assembly, an insulation support assembly and an encapsulation layer. An inner side of the silicon steel sheet assembly defines a connection hole. A winding assembly is wound on the silicon steel sheet assembly and electrically connected with a circuit board. A first extension section protrudes from the silicon steel sheet assembly into the connection hole to cover a part of the inner side. A bearing cup covers the other part of the inner side. The encapsulation layer encapsulates the insulation support assembly, the winding assembly, the silicon steel sheet assembly and the circuit board so as to achieve salt spray resistant effect.

Abstract: Provided is a semiconductor device. The semiconductor device includes a first counter latch circuit configured to receive a count code and to latch the count code according to a comparison result signal; and a second counter latch circuit configured to receive the count code from the first counter latch circuit, and to latch the count code by using a plurality of first latches. The first latches are coupled in series to each other and are configured to operate to sequentially bypass values transmitted to the respective first latches.

Abstract: Disclosed is a battery pack with improved durability and inner space efficiency to increase energy density. The battery pack includes a plurality of battery cells; a battery management unit configured to manage charging and discharging of the plurality of battery cells and including at least two printed circuit boards electrically connected to each other and arranged such that such that surfaces of the at least two printed circuit boards face each other; and an electrically insulating pack housing having an inner space in which the plurality of battery cells are accommodated and having a fixing unit being configured to fix the at least two printed circuit boards.

Abstract: Provided is a battery assembly including: a battery housing; a battery cell assembly including a plurality of battery cells which are stacked and placed in the housing and are electrically connected; and a heat dissipation resin layer, and the battery assembly has minimized cell damage due to a swelling phenomenon occurring in a battery cell and an improved module life by controlling the physical properties of the low-hardness heat dissipation resin layer.

Abstract: An antenna device according to an embodiment of the present invention includes a dielectric layer, a first radiator disposed on the dielectric layer in a first direction, a second radiator formed in a shape different from that of the first radiator and disposed on the dielectric layer in a second direction, a first transmission line which extends in the first direction to be connected to the first radiator, and a second transmission line which extends in the second direction to be connected to the second radiator, and intersects the first transmission line with being physically or electrically spaced apart therefrom.

Abstract: A display device may include a display panel including pixels, and a display panel driver which drives the display panel. The display panel driver determines whether input image data displays a white image and whether the input image data displays a moving image, and adjusts an input saturation value of the input image data based on whether the input image data displays the white image and whether the input image data displays the moving image to generate correction image data.

Abstract: A display device includes: a display area and a non-display area; a first pixel area and a second pixel area, each provided in the display area; scan lines extending in a first direction and disposed in the first pixel area and the second pixel area; first sub-scan lines extending in a second direction and disposed in the first pixel area, the second direction intersecting the first direction; second sub-scan lines extending in the second direction and disposed in the first pixel area and the second pixel area; and a pad part provided in the non-display area, the pad part being electrically connected to the first sub-scan lines and the second sub-scan lines. The scan lines are electrically connected to at least one of the first sub-scan lines and the second sub-scan lines. The first sub-scan lines do not overlap the second pixel area in a plan view.

Abstract: An electronic device able to be operated with a first state and a second state includes a substrate and electronic units. In a top view, the substrate has a first area in the first state and a second area in the second state, and the second area is greater than the first area. The electronic units are disposed on the substrate. The number of the electronic units being in a mode of ON in the second state is greater than that in the first state. The electronic device has a PPA_1 that is defined as a number of the electronic units being in the mode of ON per unit area of the substrate while in the first state, and a PPA_2 that is defined as a number of the electronic units being in the mode of ON per unit area of the substrate while in the second state, 1.5×PPA_1?PPA_2?0.5×PPA_1.

Abstract: Disclosed is a display apparatus. The display apparatus includes an input interface, a display panel, at least one memory configured to store instructions, and at least one processor configured to execute the instructions to identify an object included in an image corresponding to the image signal, adjust a dimming value of an area of the display panel corresponding to the object so that a brightness of the object is increased, and control the display panel to display the image based on the adjusted dimming value.

Abstract: According to an aspect of the present disclosure, an organic light emitting display apparatus includes an organic light emitting diode; a driving transistor which supplies a driving current to the organic light emitting diode; and a plurality of switching transistors to transmit a reference voltage and a data voltage to a gate electrode of the driving transistor, respectively. According to the present disclosure, one frame is divided into a refresh period in which a data voltage is written and a hold period in which the data voltage written in the refresh period is held. The refresh period includes an initialization period, a sampling period, a programming period, and an emission period, and the sampling period and the programming period may be separate from each other.

Abstract: An amplifier may include multiple stages, with the multiple stages arranged in a fan-out configuration. The fan-out configuration provides multiple amplified signals at multiple amplifier output nodes, which may be coupled to a shared set of downconverters. The shared downconverters may support processing of only a smaller bandwidth than the largest possible bandwidth of an input RF signal input to the amplifier. For example, the downconverters may support a bandwidth matching a smallest bandwidth of a supported RF signal. For example, when the amplifier is intended to support 5G mmWave RF signals and 5G sub-6 GHz RF signals, the downconverters may each individually support a bandwidth of carriers in the 5G sub-6 GHz RF signals but not individually support the entire bandwidth of a possible 5G mmWave RF signal.

Abstract: A memory device is provided, including a memory array, a driver circuit, and recover circuit. The memory array includes multiple memory cells. Each memory cell is coupled to a control line, a data line, and a source line and, during a normal operation, is configured to receive first and second voltage signals. The driver circuit is configured to output at least one of the first voltage signal or the second voltage signal to the memory cells. The recover circuit is configured to output, during a recover operation, a third voltage signal, through the driver circuit to at least one of the memory cells. The third voltage signal is configured to have a first voltage level that is higher than a highest level of the first voltage signal or the second voltage signal, or lower than a lowest level of the first voltage signal or the second voltage signal.

Abstract: A display device comprises a display panel including a plurality of sub-pixels defined by a plurality of gate lines and a plurality of data lines; and an auxiliary ground voltage line disposed between two adjacent data lines of the plurality of data lines.

Abstract: A pixel circuit and a display device including the same are disclosed. The pixel circuit includes a driving element including a first electrode connected to a first power line, a gate electrode connected to a first node, and a second electrode connected to a second node, a first switch element connected between a data line through which a first or second data voltage is applied and the first node, and supplies the first data voltage to the first node responsive to a first gate signal, a second switch element connected between the data line and the second node and supplies the second data voltage to the second node responsive to a second gate signal, a light-emitting element including an anode connected to the second node and a cathode connected to a second power line, and a capacitor connected between the first and second nodes.

Abstract: Often when there is a glare on a display screen the user may be able to mitigate the glare by tilting or otherwise moving the screen or changing their viewing position. However, when driving a car there are limited options for overcoming glares on the dashboard, especially when you are driving for a long distance in the same direction. Embodiments are directed to eliminating such glare. Other embodiments are related to mixed reality (MR) and filling in occluded areas.

Abstract: A method for manufacturing a semiconductor structure, including: providing a base; forming a Through Silicon Via (TSV) in the base, with a depth of the TSV being less than a thickness of the base; and forming a liner layer on a sidewall and the bottom of the TSV, and forming a conductive layer in the TSV, the liner layer including a polish-stop layer.

Abstract: Provided is a method to adjust a film stress. In one embodiment, a first film is formed on the substrate by supplying a first reactant and a second reactant sequentially and alternately in a first step, and the first film is converted into a second film by supplying a third reactant to the first film in a second step. The film stress of the second film is adjusted by controlling the ratio of the first step and the second step.

Abstract: A door locking mechanism and semiconductor container using the same include door panel, cover, and locking module. The door panel has a first stop structure. The cover and the door panel define an accommodating space for receiving the locking module. The locking module includes rotating member, holding member, and elastic member. The elastic member is disposed on the holding member and has a second stop structure near the first stop structure. The elastic member is disposed between the holding and the rotating member. The elastic member is compressed when a force is applied to the holding member, and the second stop structure detaches from a limitation state with the first stop structure for allowing a rotating operation of the rotating member. The elastic member elastically restores when the force is removed, and the second stop structure returns to the limitation state for limiting the rotating operation.

Abstract: A semiconductor device includes a substrate including an active pattern, a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer including a recess on an upper portion thereof, and a lower connection line in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line including a conductive pattern, the recess of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, and a barrier pattern between the conductive pattern and the first interlayer dielectric layer, the first interlayer dielectric layer covering a top surface of the barrier pattern.

Abstract: Reservations of resources within a dynamic workspace are made and facilitated including by pushing configurations specific to a worker for whom a reservation is made to the resource for a limited time period for the reservation. When the worker arrives for the reservation and checks in, configurations associated with the worker are obtained and pushed to the resource to configure the resource for use by the worker for a time period of the reservation. In some cases, an identity of the worker may be verified to complete the check in process for the reservation. In response to an end time of the reservation being determined, such as based on a scheduled end time for the reservation or based on a determination that the resource has gone unused for some amount of time, the configurations are removed from the resource to prepare the resource for use by a next worker.