Abstract: A clock buffer device for a memory module includes a first clock input coupled to an input of a first phase-locked loop (PLL), and a second clock input coupled to an input of a second PLL. An output of the first PLL is selectably coupled to clock output buffers, and an output of the second PLL is selectably coupled to a subset of the clock output buffers. The clock buffer device receives a first indication that a first information handling system is configured to provide a first clock signal on the first clock input but to not provide a second clock signal on the second clock input, and, in response to the indication, couples the output of the first PLL to the clock output buffers and to disables the second PLL.

Abstract: A clock buffer device for a memory module includes a first clock input coupled to an input of a first phase-locked loop (PLL), and a second clock input coupled to an input of a second PLL. An output of the first PLL is selectably coupled to clock output buffers, and an output of the second PLL is selectably coupled to a subset of the clock output buffers. The clock buffer device receives a first indication that a first information handling system is configured to provide a first clock signal on the first clock input but to not provide a second clock signal on the second clock input, and, in response to the indication, couples the output of the first PLL to the clock output buffers and to disables the second PLL.

Abstract: A clock buffer device for a memory module includes a first clock input coupled to an input of a first phase-locked loop (PLL), and a second clock input coupled to an input of a second PLL. An output of the first PLL is selectably coupled to clock output buffers, and an output of the second PLL is selectably coupled to a subset of the clock output buffers. The clock buffer device receives a first indication that a first information handling system is configured to provide a first clock signal on the first clock input but to not provide a second clock signal on the second clock input, and, in response to the indication, couples the output of the first PLL to the clock output buffers and to disables the second PLL.

Abstract: A clock buffer device for a memory module includes a first clock input coupled to an input of a first phase-locked loop (PLL), and a second clock input coupled to an input of a second PLL. An output of the first PLL is selectably coupled to clock output buffers, and an output of the second PLL is selectably coupled to a subset of the clock output buffers. The clock buffer device receives a first indication that a first information handling system is configured to provide a first clock signal on the first clock input but to not provide a second clock signal on the second clock input, and, in response to the indication, couples the output of the first PLL to the clock output buffers and to disables the second PLL.

Abstract: A clock buffer device for a memory module includes a first clock input coupled to an input of a first phase-locked loop (PLL), and a second clock input coupled to an input of a second PLL. An output of the first PLL is selectably coupled to clock output buffers, and an output of the second PLL is selectably coupled to a subset of the clock output buffers. The clock buffer device receives a first indication that a first information handling system is configured to provide a first clock signal on the first clock input but to not provide a second clock signal on the second clock input, and, in response to the indication, couples the output of the first PLL to the clock output buffers and to disables the second PLL.

Abstract: In one embodiment, a method for increasing power efficiency for an information handling system includes: monitoring, by a host service, one or more performance metrics associated with a memory device of the information handling system, the memory device including a power controller communicably coupled to a management device via a side-band bus; predicting, by the host service, an energy requirement for the memory device based on the one or more performance metrics; generating, by the host service, a power configuration profile based on the energy requirement, the power configuration profile indicating one or more power controller parameters associated with the power controller; sending, by the host service, the power configuration profile to the management device; receiving, by the management device, the power configuration profile; and modifying, by the management device and via the side-band bus, the one or more power controller parameters based on the power configuration profile.

Abstract: In one embodiment, a method for increasing power efficiency for an information handling system includes: monitoring, by a host service, one or more performance metrics associated with a memory device of the information handling system, the memory device including a power controller communicably coupled to a management device via a side-band bus; predicting, by the host service, an energy requirement for the memory device based on the one or more performance metrics; generating, by the host service, a power configuration profile based on the energy requirement, the power configuration profile indicating one or more power controller parameters associated with the power controller; sending, by the host service, the power configuration profile to the management device; receiving, by the management device, the power configuration profile; and modifying, by the management device and via the side-band bus, the one or more power controller parameters based on the power configuration profile.

Abstract: Methods, systems, and computer programs encoded on computer storage medium, performing, at first time, a calibration and configuration of a data contextual migration model, including: identifying contextual data associated with contextual inputs to a IHS, the contextual data including user contextual data, environmental context data, and system telemetry contextual data; training, based on the contextual data, the data contextual migration model, including: tagging, for each data block of a plurality of data blocks, the data block with identifiers indicating a store location of the data block; storing, based on the identifier associated with each data block, the data block at a local data store of the information handling system, at a remote data store of a remote server computing system, or both; generating a configuration policy including configuration rules, the configuration rules for prioritizing pre-loading of a subset of the data blocks to be provided at the information handling system.

Abstract: A system and method for ensuring information present in volatile memory is moved to persistent memory before power is removed. An information handling system stores a time value corresponding to an amount of time for power to be supplied to the information handling system after a signal is received to power down the information handling system. An embedded controller determines the amount of information present in volatile memory, determines an amount of time needed to move the information to persistent memory, and adjusts the time value as needed to ensure power is supplied to the system until the information has been moved to persistent memory.

Abstract: Methods, systems, and computer programs encoded on computer storage medium, performing, at first time, a calibration and configuration of a data contextual migration model, including: identifying contextual data associated with contextual inputs to a IHS, the contextual data including user contextual data, environmental context data, and system telemetry contextual data; training, based on the contextual data, the data contextual migration model, including: tagging, for each data block of a plurality of data blocks, the data block with identifiers indicating a store location of the data block; storing, based on the identifier associated with each data block, the data block at a local data store of the information handling system, at a remote data store of a remote server computing system, or both; generating a configuration policy including configuration rules, the configuration rules for prioritizing pre-loading of a subset of the data blocks to be provided at the information handling system.

Abstract: A system and method for ensuring information present in volatile memory is moved to persistent memory before power is removed. An information handling system stores a time value corresponding to an amount of time for power to be supplied to the information handling system after a signal is received to power down the information handling system. An embedded controller determines the amount of information present in volatile memory, determines an amount of time needed to move the information to persistent memory, and adjusts the time value as needed to ensure power is supplied to the system until the information has been moved to persistent memory.

Abstract: In some implementations a logic device, such as an embedded controller, automatically configures a universal serial bus (USB) Type-C port by connecting the USB Type-C port to appropriate input/output (I/O) signals. For example, the logic device may receive a notification that an external device is connected to a USB Type-C port of a computing device. The logic device may receive data from a port controller over an internal communication bus associated with the USB Type-C port. Based at least in part on the data, the logic device may determine one or more types of signals that the external device is configured to send, receive, or send and receive. The logic device may instruct a cross-point switch to connect the USB Type-C port to one or more signal paths in the computing device to enable the external device to send/receive the one or more types of signals.

Abstract: In some implementations a logic device, such as an embedded controller, automatically configures a universal serial bus (USB) Type-C port by connecting the USB Type-C port to appropriate input/output (I/O) signals. For example, the logic device may receive a notification that an external device is connected to a USB Type-C port of a computing device. The logic device may receive data from a port controller over an internal communication bus associated with the USB Type-C port. Based at least in part on the data, the logic device may determine one or more types of signals that the external device is configured to send, receive, or send and receive. The logic device may instruct a cross-point switch to connect the USB Type-C port to one or more signal paths in the computing device to enable the external device to send/receive the one or more types of signals.

Abstract: In some implementations a logic device, such as an embedded controller, automatically configures a universal serial bus (USB) Type-C port by connecting the USB Type-C port to appropriate input/output (I/O) signals. For example, the logic device may receive a notification that an external device is connected to a USB Type-C port of a computing device. The logic device may receive data from a port controller over an internal communication bus associated with the USB Type-C port. Based at least in part on the data, the logic device may determine one or more types of signals that the external device is configured to send, receive, or send and receive. The logic device may instruct a cross-point switch to connect the USB Type-C port to one or more signal paths in the computing device to enable the external device to send/receive the one or more types of signals.

Abstract: A system, method, and computer-readable medium are disclosed for optimizing performance of an information handling system comprising: profiling a plurality of applications based upon executing the applications on a particular information handling system, the particular information handling system including a tiered data and instruction cache architecture; identifying which of the plurality of applications are contained within a set of frequently used applications for a particular user; and, updating a tiered data and instruction cache architecture based upon the profiling.

Abstract: Host memory buffer is dynamically adjusted based on performance. As memory pages are accessed, one or more counts of the memory pages are maintained. If the counts indicate some of the memory pages are identical, then a portion of host system memory allocated to buffer cache may be reduced or decremented in response to repetitive access. However, if the counts indicate different memory pages are accessed, then the host system memory allocated to the buffer cache may be increased or incremented.

Abstract: In some implementations a logic device, such as an embedded controller, automatically configures a universal serial bus (USB) Type-C port by connecting the USB Type-C port to appropriate input/output (I/O) signals. For example, the logic device may receive a notification that an external device is connected to a USB Type-C port of a computing device. The logic device may receive data from a port controller over an internal communication bus associated with the USB Type-C port. Based at least in part on the data, the logic device may determine one or more types of signals that the external device is configured to send, receive, or send and receive. The logic device may instruct a cross-point switch to connect the USB Type-C port to one or more signal paths in the computing device to enable the external device to send/receive the one or more types of signals.

Abstract: Host memory buffer is dynamically adjusted based on performance. As memory pages are accessed, one or more counts of the memory pages are maintained. If the counts indicate some of the memory pages are identical, then a portion of host system memory allocated to buffer cache may be reduced or decremented in response to repetitive access. However, if the counts indicate different memory pages are accessed, then the host system memory allocated to the buffer cache may be increased or incremented.

Abstract: Methods and systems are disclosed for power usage level management of blades installed in blade servers. When a new blade added is to a blade server, possible power usage levels for the new blade are assessed to determine possible effects on the total power usage level of the chassis. By assessing the different power usage levels, the chassis controller can then make intelligent decisions as to the power usage levels at which new blades will be allowed to operate while still keeping within chassis power supply capabilities. Blade power usage levels can be based upon a variety of considerations, including processor performance modes and blade configuration options.