Abstract: A package structure and a manufacturing method for the same are provided. The package structure includes a circuit, a mold sealing layer, a conductive metal board, and a conductive layer. The circuit board includes a substrate and a first electronic element disposed on the substrate. The mold sealing layer is disposed on the substrate and covers the first electronic element. The mold sealing layer has a top surface, a bottom surface corresponding to the top surface, and a side surface connected between the top surface and the bottom surface. The conductive metal board is disposed on the top surface and adjacent to the first electronic element. The conductive layer is disposed on the side surface and electrically connected to the conductive metal board. The conductive metal board and the conductive layer are each an independent component.

Abstract: A package structure and a manufacturing method for the same are provided. The package structure includes a circuit, a mold sealing layer, a conductive metal board, and a conductive layer. The circuit board includes a substrate and a first electronic element disposed on the substrate. The mold sealing layer is disposed on the substrate and covers the first electronic element. The mold sealing layer has a top surface, a bottom surface corresponding to the top surface, and a side surface connected between the top surface and the bottom surface. The conductive metal board is disposed on the top surface and adjacent to the first electronic element. The conductive layer is disposed on the side surface and electrically connected to the conductive metal board. The conductive metal board and the conductive layer are each an independent component.

Abstract: A package structure and a manufacturing method thereof are provided. The package structure includes a circuit board, a barrier structure and a molding layer. The circuit board includes a substrate and a component disposed on the substrate. The substrate includes a molding area and a non-molding area, and the component is disposed on the molding area. The barrier structure is disposed on the substrate and located between the molding area and the non-molding area. The barrier structure has a first predetermined height. The molding layer is disposed on the molding area and covers the component. The molding layer has a second predetermined height. The first predetermined height of the barrier structure is less than or equal to the second predetermined height of the molding layer.

Abstract: A package structure and a manufacturing method for the same are provided. The package structure includes a circuit, a mold sealing layer, a conductive metal board, and a conductive layer. The circuit board includes a substrate and a first electronic element disposed on the substrate. The mold sealing layer is disposed on the substrate and covers the first electronic element. The mold sealing layer has a top surface, a bottom surface corresponding to the top surface, and a side surface connected between the top surface and the bottom surface. The conductive metal board is disposed on the top surface and adjacent to the first electronic element. The conductive layer is disposed on the side surface and electrically connected to the conductive metal board. The conductive metal board and the conductive layer are each an independent component.

Abstract: A package structure and a manufacturing method thereof are provided. The package structure includes a circuit board, a barrier structure and a molding layer. The circuit board includes a substrate and a component disposed on the substrate. The substrate includes a molding area and a non-molding area, and the component is disposed on the molding area. The barrier structure is disposed on the substrate and located between the molding area and the non-molding area. The barrier structure has a first predetermined height. The molding layer is disposed on the molding area and covers the component. The molding layer has a second predetermined height. The first predetermined height of the barrier structure is less than or equal to the second predetermined height of the molding layer.

Abstract: A portable electronic apparatus is provided which includes a first housing, a second housing, a control unit, a display unit, and a wireless communication device. The two housings are rotatably coupled to each other. The control unit is accommodated in the first housing. The display unit is accommodated in the second housing and is connected to the control unit. The wireless communication device is accommodated in the second housing and has a wireless communication module and an antenna. The wireless communication module is connected to the control unit and the antenna, and is configured to perform wireless communication through the antenna under control of the control unit.

Abstract: A molded radio-frequency (RF) structure with electromagnetic shielding includes a substrate layer, an RF layer, a molded layer and a metal layer. The RF element is disposed on the substrate layer. The molded layer is located on the substrate layer and overlays the RF element. The metal layer is coated on the molded layer, and has an opening located above the RF element.

Abstract: The invention discloses a testing system and a testing method, suitable for testing a DUT with double-sided signal pins. The testing system includes a testing platform and a pick-and-place device. The testing platform includes an electromagnetic shielding chamber and a test-bench module. The electromagnetic shielding chamber has an opening. The test-bench module is disposed in-between the electromagnetic shielding chamber. The pick-and-place device is movably disposed above the testing platform. The pick-and-place device includes an electromagnetic shielding cap and a signal transmission structure. When the pick-and-place device places the DUT on the test-bench module, the electromagnetic shielding cap cooperates with the electromagnetic shielding chamber of the testing platform to form an isolated space for isolating the DUT, and furthermore, the signal pin disposed on an upper surface of the DUT can be electrically connected to the test-bench module through the signal transmission structure.

Abstract: A wafer level chip scale packaging structure and the method of fabricating the same are provided to form a sacrificial layer below the bump using a normal semiconductor process. The bump is used to connect the signals between the Si wafer and the PCB. The interface between the sacrificial layer and the adjacent layers is the weakest part in the whole structure. When the stress applied to the bump is overloaded, the interface between the sacrificial layer and the adjacent layers will crash to remove the stress generated by different thermal expansion coefficients of the Si wafer and the PCB. The sacrificial layer would help avoid the crash occurring to the bump to protect the electrical conduction between the Si wafer and the PCB.

Abstract: A portable electronic apparatus is provided which includes a first housing, a second housing, a control unit, a display unit, and a wireless communication device. The two housings are rotatably coupled to each other. The control unit is accommodated in the first housing. The display unit is accommodated in the second housing and is connected to the control unit. The wireless communication device is accommodated in the second housing and has a wireless communication module and an antenna. The wireless communication module is connected to the control unit and the antenna, and is configured to perform wireless communication through the antenna under control of the control unit.

Abstract: The invention discloses a testing system and a testing method, suitable for testing a DUT with double-sided signal pins. The testing system includes a testing platform and a pick-and-place device. The testing platform includes an electromagnetic shielding chamber and a test-bench module. The electromagnetic shielding chamber has an opening. The test-bench module is disposed in-between the electromagnetic shielding chamber. The pick-and-place device is movably disposed above the testing platform. The pick-and-place device includes an electromagnetic shielding cap and a signal transmission structure. When the pick-and-place device places the DUT on the test-bench module, the electromagnetic shielding cap cooperates with the electromagnetic shielding chamber of the testing platform to form an isolated space for isolating the DUT, and furthermore, the signal pin disposed on an upper surface of the DUT can be electrically connected to the test-bench module through the signal transmission structure.

Abstract: A wafer level packaging structure with inductors and manufacture method thereof. The method comprises providing a substrate, having several inductors, forming conductive lines and holes to connect the inductors and the wafer, and bonding the substrate and the wafer via bonding pads. Therefore, there are air gaps between the inductors and the wafer, thereby reducing the inductor's dispassion loss and increasing the inductor's quality factor. In addition, the inductors having a high quality factor can be integrated in the wafer containing active/passive components.

Abstract: A packaging structure with protective layers and a packaging method thereof are provided. A protective layer is formed on the surface and the pre-dicing line of the wafer to protect the chip and the die during the wafer grinding process, so as to prevent the wafer from being damaged due to the collision during the transportation process, and thereby reinforcing the mechanical strength of the wafer and the chip, which is useful for the subsequent packaging process.

Abstract: A wafer level chip scale packaging structure and the method of fabricating the same are disclosed to form a sacrificial layer below the bump using a normal semiconductor process. The bump is used to connect the signals between the Si wafer and the PCB. The interface between the sacrificial layer and the PCB is the weakest part in the whole structure. When the stress applied to the bump is overloaded, the interface between the sacrificial layer and the adjacent layers will peel or the sacrificial layer material will crash to remove the stress generated by different thermal expansion coefficients of the Si wafer and the PCB. The sacrificial layer would help avoid the crash occurring to the bump to protect the electrical conduction between the Si wafer and the PCB.

Abstract: A wafer level packaging structure with inductors and manufacture method thereof. The method comprises providing a substrate, having several inductors, forming conductive lines and holes to connect the inductors and the wafer, and bonding the substrate and the wafer via bonding pads. Therefore, there are air gaps between the inductors and the wafer, thereby reducing the inductor's dispassion loss and increasing the inductor's quality factor. In addition, the inductors having a high quality factor can be integrated in the wafer containing active/passive components.

Abstract: A wafer level chip scale packaging structure and the method of fabricating the same are provided to form a sacrificial layer below the bump using a normal semiconductor process. The bump is used to connect the signals between the Si wafer and the PCB. The interface between the sacrificial layer and the adjacent layers is the weakest part in the whole structure. When the stress applied to the bump is overloaded, the interface between the sacrificial layer and the adjacent layers will crash to remove the stress generated by different thermal expansion coefficients of the Si wafer and the PCB. The sacrificial layer would help avoid the crash occurring to the bump to protect the electrical conduction between the Si wafer and the PCB.

Abstract: A wafer level chip scale packaging structure and the method of fabricating the same are disclosed to form a sacrificial layer below the bump using a normal semiconductor process. The bump is used to connect the signals between the Si wafer and the PCB. The interface between the sacrificial layer and the PCB is the weakest part in the whole structure. When the stress applied to the bump is overloaded, the interface between the sacrificial layer and the PCB will crash to remove the stress generated by different thermal expansion coefficients of the Si wafer and the PCB. The sacrificial layer would help avoid the crash occurring to the bump to protect the electrical conduction between the Si wafer and the PCB.

Abstract: A wafer level chip scale packaging structure and the method of fabricating the same are disclosed to form a sacrificial layer below the bump using a normal semiconductor process. The bump is used to connect the signals between the Si wafer and the PCB. The interface between the sacrificial layer and the PCB is the weakest part in the whole structure. When the stress applied to the bump is overloaded, the interface between the sacrificial layer and the PCB will crash to remove the stress generated by different thermal expansion coefficients of the Si wafer and the PCB. The sacrificial layer would help avoid the crash occurring to the bump to protect the electrical conduction between the Si wafer and the PCB.

Abstract: A wafer level chip scale packaging structure and the method of fabricating the same are disclosed to form a sacrificial layer below the bump using a normal semiconductor process. The bump is used to connect the signals between the Si wafer and the PCB. The interface between the sacrificial layer and the PCB is the weakest part in the whole structure. When the stress applied to the bump is overloaded, the interface between the sacrificial layer and the PCB will crash to remove the stress generated by different thermal expansion coefficients of the Si wafer and the PCB. The sacrificial layer would help avoid the crash occurring to the bump to protect the electrical conduction between the Si wafer and the PCB.

Abstract: A flexible electronic/optical interconnection film assembly which includes a flexible waveguide film laminated to a flexible electrical film, such as a flexible PCB. The flexible waveguide film has embedded internal waveguide capable of total internal reflection such that optical transmission between two IC elements can be achieved through the use of laser diode transmitters and photodetector receivers. A flexible electrical film that is laminated to the flexible waveguide film may have a plurality of metal interconnect lines formed therein for providing electrical communication. A thin metal trace layer and a plurality of conductive pads which are formed from the thin metal trace layer may be formed on top of the flexible waveguide film for providing electrical communication with active opto-electronic devices mounted on top of the flexible waveguide film.