Abstract: A semiconductor device includes: M*1st conductors in a first layer of metallization (M*1st layer) and being aligned correspondingly along different corresponding ones of alpha tracks and representing corresponding inputs of a cell region in the semiconductor device; and M*2nd conductors in a second layer of metallization (M*2nd layer) aligned correspondingly along beta tracks, and the M*2nd conductors including at least one power grid (PG) segment and one or more of an output pin or a routing segment; and each of first and second ones of the input pins having a length sufficient to accommodate at most two access points; each of the access points of the first and second input pins being aligned to a corresponding different one of first to fourth beta tracks; and the PG segment being aligned with one of the first to fourth beta tracks.

Abstract: A system and method for alignment. In some embodiments, the method includes measuring a first offset, the first offset being an offset along a first direction between a first alignment mark and a second alignment mark, the first alignment mark being an alignment mark on a first edge of a source die, the second alignment mark being an alignment mark on a target wafer, and the first direction being substantially parallel to the first edge of the source die.

Abstract: An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.

Abstract: Embodiments of the present invention provide systems and methods to enable secure communication between a host processor and external real time counter (RTC) logic. In an embodiment, the host processor generates a message including a command to an external device containing the RTC. The external device verifies a Message Authentication Code (MAC) included in the message and responds to the command. Embodiments of the present invention advantageously provide a dedicated power domain for the external RTC logic while guarding against third party attacks on the RTC logic and the communication between the RTC logic and the host processor.

Abstract: An automatic lens cutting machine (1) includes a body portion, a carrying device (10), a cutting device (20), a take out device (30), a power device and an electrical control portion. The take out device is mounted adjacent to the carrying device, and comprises a shelf (31) mounted on a base (40) of the body portion and a lens receiving device (34) disposed above the shelf. The lens receiving device has a plurality of rows of tubular rings. Each row has a plurality of rings. The rings receive unseparated lenses (90) on a semi-finished lens assembly (9) therein when the automatic lens cutting machine is in operation, and retain the separated lenses therein after the semi-finished lens assembly is subject to a cutting operation.

Abstract: An embodiment of a bus management device permits scheduling of transactions to allow concurrent execution of the transactions. Data bus usage is scheduled by setting shift register bits. Each position in the shift register corresponds to one clock cycle. When a current transaction is in a data phase, the value in the shift register is used to determine when to begin a control phase of the next transaction so that a desired number of idle clock cycles are present between data bus usage time periods for successive transactions.