Abstract: A display device includes a substrate, a first transparent pattern disposed on the substrate, where a first opening is defined through the first transparent pattern, and a first light absorbing layer overlapping a side surface of the first transparent pattern defining the first opening, where the first light absorbing layer includes a metal oxide including a first metal element, which is selected from molybdenum (Mo), copper (Cu) and chromium (Cr), and a second metal element of Group 15, and the first light absorbing layer has a thickness in a range of about 500 ? to about 10000 ?.

Abstract: A virtual machine backup method, performed by a first host, includes: capturing a request to write data from a virtual machine to a hard disk image file, wherein the request includes written data and input and output location information, copying the written data to a temporary storage area, calculating a first key of the written data, storing the first key, the input and output location information into a first resource location structure, pausing an operation of the virtual machine and generating a second resource location structure according to the first resource location structure, the first key and a second key, and outputting a backup data set to a second host according to the second resource location structure, wherein the backup data set includes the second resource location structure and only one of existing data and the written data when the first key and the second key are the same.

Abstract: An integrated circuit includes a first-voltage power rail and a second-voltage power rail in a first connection layer, and includes a first-voltage underlayer power rail and a second-voltage underlayer power rail below the first connection layer. Each of the first-voltage and second-voltage power rails extends in a second direction that is perpendicular to a first direction. Each of the first-voltage and second-voltage underlayer power rails extends in the first direction. The integrated circuit includes a first via-connector connecting the first-voltage power rail with the first-voltage underlayer power rail, and a second via-connector connecting the second-voltage power rail with the second-voltage underlayer power rail.

Abstract: An apparatus is disclosed which includes an ultraviolet laser and at least one reflective mirror having a substrate which is made from beryllium, an aluminum metal matrix, or silicon carbide. The at least one mirror is adapted to reflect a laser beam generated from the ultraviolet laser, which can then be used on a silicon film used in the production of an electronic display. The laser beam can be used to anneal the silicon film, or in a laser lift-off process for separating the silicon film from a temporary substrate upon which the silicon film was mounted.

Abstract: Provided are an electroluminescent device, a method of manufacturing the same, and a display device including the same, the electroluminescent device including a first electron auxiliary layer, a first light emitting layer, and a first electrode disposed on a first surface of a transparent electrode; and a second electron auxiliary layer, a second light emitting layer, and a second electrode disposed on a second surface of the transparent electrode, wherein the first electron auxiliary layer and the second electron auxiliary layer each include a plurality of zinc oxide nanoparticles, a ratio (t1/t0) of a thickness (t1) of the first electron auxiliary layer to a thickness (t0) of the transparent electrode and a ratio (t2/t0) of a thickness (t2) of the second electron auxiliary layer to the thickness (t0) of the transparent electrode are each in the range of about 0.1 to about 4.0.

Abstract: A display panel includes a color conversion panel and a light emitting panel, the light emitting panel includes a light emitting device that includes a first electrode, a second electrode, and a blue light emitting unit that includes an organic light emitting layer and is disposed between the first electrode and the second electrode and is configured to emit blue light. The color conversion panel includes a color conversion layer including at least two color conversion regions, and optionally, a partition wall defining that at least two regions, wherein the color conversion region includes a first region corresponding to a green pixel, a second region corresponding to a red pixel, and optionally a third region corresponding to a blue pixel.

Abstract: A semiconductor device includes a plurality of standard cells. The plurality of standard cells include a first group of standard cells arranged in a first row extending in a row direction and a second group of standard cells arranged in a second row extending in the row direction. The first group of standard cells and the second group of standard cells are arranged in a column direction. A cell height of the first group of standard cells in the column direction is different from a cell height of the second group of standard cells in the column direction.

Abstract: An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.

Abstract: An electroluminescent device including a first electrode and a second electrode facing each other; a light emitting layer disposed between the first electrode and the second electrode; and an electron transport layer disposed between the light emitting layer and the second electrode. The light emitting layer includes a plurality of semiconductor nanoparticles, and the electron transport layer includes a plurality of zinc oxide nanoparticles, the zinc oxide nanoparticles further include magnesium and gallium.

Abstract: A semiconductor device includes a transistor layer, a first via layer over the transistor layer, a first metallization layer over the first via layer, the first metallization layer including first conductors having long axes extending substantially in a first direction, a second via layer over the first metallization layer, and a conductive deep via extending in the second via layer, the first metallization layer, and the first via layer. The first conductors represent a majority of conductive material in the first metallization layer, and a size of the deep via in the first direction in the first metallization layer is substantially less than a minimum length of the first conductors in the first metallization layer.

Abstract: Disclosed is a technique related to a method and apparatus for generating a preamble and a data frame for wireless communication, and to a synchronization estimation method using the preamble. According to the technique, a method for generating a frame for wireless communication is disclosed, wherein the method comprises: a step of generating a modified sequence using a first base sequence for synchronization estimation; and a step of allocating the first base sequence and the modified sequence to the frequency domain of a first timeslot to generate a preamble. The modified sequence includes a complex conjugated sequence of the first base sequence or a sequence having a code different from that of the first base sequence.

Abstract: A display device includes a circuit layer and a display element layer on the circuit layer. The display element layer includes a light-emitting element and a pixel-defining film, through which a pixel opening is defined, and the light-emitting element includes a first electrode exposed through the pixel opening, a second electrode disposed opposite to the first electrode, and a light-emitting layer disposed between the first electrode and the second electrode. The first electrode includes a metal layer and a graphene layer disposed on an upper surface of the metal layer, and the metal layer and the graphene layer each have a hexagonal closed packed structure.

Abstract: Packaged semiconductor devices including high-thermal conductivity molding compounds and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution structure; a first die over and electrically coupled to the first redistribution structure; a first through via over and electrically coupled to the first redistribution structure; an insulation layer extending along the first redistribution structure, the first die, and the first through via; and an encapsulant over the insulation layer, the encapsulant surrounding portions of the first through via and the first die, the encapsulant including conductive fillers at a concentration ranging from 70% to about 95% by volume.

Abstract: A coating composition, coating glass and a method for preparation thereof, and a cooking appliance including the coating class are described. The coating composition includes a coating material and a heat conductive oxide nano powder that is 5 to 10 wt % with respect to a weight of the coating material. The coating composition provides an excellent infrared reflective function, a high transmittance, and an excellent cleaning performance.

Abstract: An integrated circuit includes a cell layer including a first cell and a second cell, a first metal layer over the cell layer and having a first conductive feature, a second metal layer over the first metal layer and having a second conductive feature, and a first via between the first metal layer and the second metal layer and connecting the first conductive feature to the second conductive feature. The first conductive feature spans over a boundary between the first and second cells, and has a lengthwise direction along a first direction. The second conductive feature spans over the boundary between the first and second cells, and has a lengthwise direction along a second direction that is perpendicular to the first direction.

Abstract: In an embodiment, a device includes: a first integrated circuit die including a first device layer and a first front-side interconnect structure, the first front-side interconnect structure including first interconnects interconnecting first devices of the first device layer; a second integrated circuit die including a second device layer and a second front-side interconnect structure, the second front-side interconnect structure including second interconnects interconnecting second devices of the second device layer; and an interposer bonded to a back-side of the first integrated circuit die and to a back-side of the second integrated circuit die, the interposer including a die-to-die interconnect structure, the die-to-die interconnect structure including a pillar, the first integrated circuit die overlapping the pillar.

Abstract: A method of generating an IC layout diagram includes abutting a first row of cells with a second row of cells along a border, the first row including first and second active sheets, the second row including third and fourth active sheets, the active sheets extending along a row direction and having width values. The active sheets are overlapped with first through fourth back-side via regions, the first active sheet width value is greater than the third active sheet width value, a first back-side via region width values is greater than a third back-side via region width value, and a value of a distance from the first active sheet to the border is less than a minimum spacing rule for metal-like defined regions. At least one of abutting the first row with the second row or overlapping the active sheets with the back-side via regions is performed by a processor.

Abstract: An integrated circuit (IC) package includes a logic die, a substrate, a memory die positioned between the logic die and the substrate, and a power distribution structure configured to electrically couple the logic die to the substrate. The power distribution structure includes a plurality of conductive segments positioned between the logic die and the memory die, a plurality of bump structures positioned between the memory die and the substrate, and a plurality of through-silicon vias (TSVs) electrically coupled to the plurality of conductive segments and the plurality of bump structures, and a TSV of the plurality of TSVs extends through, and is electrically isolated from, a memory macro of the memory die.

Abstract: A method of manufacturing a semiconductor device includes forming via structures in a first via layer over a transistor layer, the forming the via structures in the first via layer including forming a first via structure in the first via layer, the first via structure being included in a first deep via arrangement; forming conductive segments in a first metallization layer over the first via layer, the forming the conductive segments in the first metallization layer including forming M_1st routing segments at least a majority of which, relative to a first direction, have corresponding long axes with lengths which at least equal if not exceed a first permissible minimum value for routing segments in the first metallization layer; and forming an M_1st interconnection segment having a long axis which is less than the first permissible minimum value, the M_1st interconnection segment being included in the first deep via arrangement.

Abstract: An integrated circuit (IC) includes first through fourth nano-sheet structures extending in a first direction and having respective first through fourth widths along a second direction perpendicular to the first direction, and first through fourth via structures electrically connected to corresponding ones of the first through fourth nano-sheet structures. The second width has a value greater than that of the third width. A width of the second via structure along the second direction has a value greater than that of a width of the third via structure along the second direction. The second and third nano-sheet structures are positioned between the first and fourth nano-sheet structures. The second and third via structures are configured to electrically connect the second and third nano-sheet structures to a first portion of a back-side power distribution structure configured to carry one of a power supply voltage or a reference voltage.