Abstract: Mechanisms are provided for extending cache for an external storage system into individual servers. Certain servers may have cards with cache in the form of dynamic random access memory (DRAM) and non-volatile storage, such as flash memory or solid-state drives (SSDs), which may be viewed as actual extensions of the external storage system. In this way, the storage system is distributed across the storage area network (SAN) into various servers. Several new semantics are used in communication between the cards and the storage system to keep the read caches coherent.

Abstract: Mechanisms are provided for extending cache for an external storage system into individual servers. Certain servers may have cards with cache in the form of dynamic random access memory (DRAM) and non-volatile storage, such as flash memory or solid-state drives (SSDs), which may be viewed as actual extensions of the external storage system. In this way, the storage system is distributed across the storage area network (SAN) into various servers. Several new semantics are used in communication between the cards and the storage system to keep the read caches coherent.

Abstract: A storage device is provided for direct memory access. A controller of the storage device performs a mapping of a window of memory addresses to a logical block addressing (LBA) range of the storage device. Responsive to receiving from a host a write request specifying a write address within the window of memory addresses, the controller initializes a first memory buffer in the storage device and associates the first memory buffer with a first address range within the window of memory addresses such that the write address of the request is within the first address range. The controller writes to the first memory buffer based on the write address. Responsive to the buffer being full the controller persists contents of the first memory buffer to the storage device using logical block addressing based on the mapping.

Abstract: A storage device is provided for direct memory access. A controller of the storage device performs a mapping of a window of memory addresses to a logical block addressing (LBA) range of the storage device. Responsive to receiving from a host a write request specifying a write address within the window of memory addresses, the controller initializes a first memory buffer in the storage device and associates the first memory buffer with a first address range within the window of memory addresses such that the write address of the request is within the first address range. The controller writes to the first memory buffer based on the write address. Responsive to the buffer being full, the controller persists contents of the first memory buffer to the storage device using logical block addressing based on the mapping.

Abstract: A first interconnect card is configured, wherein a first controller is included in the first interconnect card. A second interconnect card coupled to the first interconnect card is configured, wherein a second controller is included in the second interconnect card. In response to a failure of the first controller included in the first interconnect card, the first interconnect card is controlled via the second controller included in the second interconnect card. In response to a failure of the second controller included in the second interconnect card, the second interconnect card is controlled via the first controller included in the first interconnect card.

Abstract: A storage device is provided for direct memory access. A controller of the storage device performs a mapping of a window of memory addresses to a logical block addressing (LBA) range of the storage device. Responsive to receiving from a host a write request specifying a write address within the window of memory addresses, the controller initializes a first memory butler in the storage device and associates the first memory buffer with a first address range within the window of memory addresses such that the write address of the request is within the first address range. The controller writes to the first memory buffer based on the write address. Responsive to the buffer being full, the controller persists contents of the first memory buffer to the storage device using logical block addressing based on the mapping.

Abstract: A method and tool for forming decorative picots is provided. The tool comprises a triangular substrate having a base and two sides intersecting at an apex, indicia defining a centerline extending from the apex to the midpoint of the base, and indicia defining one or more guidelines extending from one side of the substrate to the other, parallel to the base. The method comprises placing the substrate on a rectangular strip of fabric having a width twice its height, aligning the substrate on the fabric such that the apex is positioned at the midpoint of the top edge of the fabric and the bottom edge is positioned parallel to the base of the substrate, folding the top edges of the fabric over the substrate to align with the centerline and applying an iron to the folded fabric to crease the fold.

Abstract: Mechanisms are provided for extending cache for an external storage system into individual servers. Certain servers may have cards with cache in the form of dynamic random access memory (DRAM) and non-volatile storage, such as flash memory or solid-state drives (SSDs), which may be viewed as actual extensions of the external storage system. In this way, the storage system is distributed across the storage area network (SAN) into various servers. Several new semantics are used in communication between the cards and the storage system to keep the read caches coherent.

Abstract: A method and tool for forming decorative picots is provided. The tool comprises a triangular substrate having a base and two sides intersecting at an apex, indicia defining a centerline extending from the apex to the midpoint of the base, and indicia defining one or more guidelines extending from one side of the substrate to the other, parallel to the base. The method comprises placing the substrate on a rectangular strip of fabric having a width twice its height, aligning the substrate on the fabric such that the apex is positioned at the midpoint of the top edge of the fabric and the bottom edge is positioned parallel to the base of the substrate, folding the top edges of the fabric over the substrate to align with the centerline and applying an iron to the folded fabric to crease the fold.

Abstract: A storage device comprising a storage medium having a plurality of sectors and a superset format. Each sector includes a header, a data section and a trailer, the data section sized to contain a number of bytes per sector equal to or greater than a maximum of subset formats to be supported. Meta data in a non-user portion of the storage medium includes a flag for indicating a subset format such that each sector is formatted to store less than the number of bytes.

Abstract: A method and apparatus that prevents data corruption and power supply failure caused by device connection transition on an active SCSI bus is provided. A bus initiator pauses communication on the SCSI bus such that only communication by the bus initiator is allowed over the data communication bus. All other communication between peripheral devices attached to the data communication bus is paused. A shutdown signal from the bus initiator is transmitted over the data communication bus to a power controller, which eliminates power to a device slot corresponding to the received shutdown signal. After a connection transition of an electrical device in the device slot, a power reset signal is transmitted from the bus initiator over the data communication bus to the power controller, which then restores power to the device slot upon receiving the reset power signal.

Abstract: A write cache operation builder for use in building a write operation for writing data from a cache to a disk drive in a computer system is disclosed. The write cache operation builder is built from a CMS of a DASD. It converts the CMS entries of the CMS into a FIFO entry and scans the FIFO entry in order to calculate a write operation comprising the largest number of sectors of data. The write cache operation builder may be implemented via hardware or software.