Patents by Inventor Lee D. Whetsel, Jr.
Lee D. Whetsel, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 6898544Abstract: A test cell (12) provides boundary scan testing in an integrated circuit (10). The test cell (12) comprises two memories, a flip-flop (24) and a latch (26), for storing test data. A first multiplexer (22) selectively connects one of a plurality of inputs to the flip-flop (24). The input of the latch (26) is connected to output of the flip-flop (24). The output of the latch (26) is connected to one input of a multiplexer (28), the second input to the multiplexer (28) being a data input (DIN) signal. A control bus (17) is provided for controlling the multiplexers (22, 28), flip-flop (24) and latch (26). The test cell allows input data to be observed and output data to be controlled simultaneously.Type: GrantFiled: April 6, 2004Date of Patent: May 24, 2005Assignee: Texas Instruments IncorporatedInventor: Lee D. Whetsel, Jr.
-
Patent number: 6813738Abstract: A test cell (12) provides boundary scan testing in an integrated circuit (10). The test cell (12) comprises two memories, a flip-flop (24) and a latch (26), for storing test data. A first multiplexer (22) selectively connects one of a plurality of inputs to the flip-flop (24). The input of the latch (26) is connected to output of the flip-flop (24). The output of the latch (26) is connected to one input of a multiplexer (28), the second input to the multiplexer (28) being a data input (DIN) signal. A control bus (17) is provided for controlling the multiplexers (22, 28), flip-flop (24) and latch (26). The test cell allows input data to be observed and output data to be controlled simultaneously.Type: GrantFiled: October 25, 2002Date of Patent: November 2, 2004Assignee: Texas Instruments IncorporatedInventor: Lee D. Whetsel, Jr.
-
Patent number: 6611934Abstract: A test cell (12) provides boundary scan testing in an integrated circuit (10). The test cell (12) comprises two memories, a flip-flop (24) and a latch (26), for storing test data. A first multiplexer (22) selectively connects one of a plurality of inputs to the flip-flop (24). The input of the latch (26) is connected to output of the flip-flop (24). The output of the latch (26) is connected to one input of a multiplexer (28), the second input to the multiplexer (28) being a data input (DIN) signal. A control bus (17) is provided for controlling the multiplexers (22, 28), flip-flop (24) and latch (26). The test cell allows input data to be observed and output data to be controlled simultaneously.Type: GrantFiled: July 3, 2001Date of Patent: August 26, 2003Assignee: Texas Instruments IncorporatedInventor: Lee D. Whetsel, Jr.
-
Patent number: 6304987Abstract: A test cell (12) provides boundary scan testing in an integrated circuit (10). The test cell (12) comprises two memories, a flip-flop (24) and a latch (26), for storing test data. A first multiplexer (22) selectively connects one of a plurality of inputs to the flip-flop (24). The input of the latch (26) is connected to output of the flip-flop (24). The output of the latch (26) is connected to one input of a multiplexer (28), the second input to the multiplexer (28) being a data input (DIN) signal. A control bus (17) is provided for controlling the multiplexers (22, 28), flip-flop (24) and latch (26). The test cell allows input data to be observed and output data to be controlled simultaneously.Type: GrantFiled: March 9, 2000Date of Patent: October 16, 2001Assignee: Texas Instruments IncorporatedInventor: Lee D. Whetsel, Jr.
-
Patent number: 6085344Abstract: A serial scan path communication architecture includes a plurality of circuits (30), some of which may include a memory (36). A memory access controller (38) is included on circuits with a memory (36) such that serial data may be written to and written from the memories without having to repetitively cycle through multiple shift operations.Type: GrantFiled: September 23, 1997Date of Patent: July 4, 2000Assignee: Texas Instruments IncorporatedInventors: Lee D. Whetsel, Jr., Benjamin H. Ashmore, Jr.
-
Patent number: 6081916Abstract: A test cell (12) provides boundary scan testing in an integrated circuit (10). The test cell (12) comprises two memories, a flip-flop (24) and a latch (26), for storing test data. A first multiplexer (22) selectively connects one of a plurality of inputs to the flip-flop (24). The input of the latch (26) is connected to output of the flip-flop (24). The output of the latch (26) is connected to one input of a multiplexer (28), the second input to the multiplexer (28) being a data input (DIN) signal. A control bus (17) is provided for controlling the multiplexers (22, 28), flip-flop (24) and latch (26). The test cell allows input data to be observed and output data to be controlled simultaneously.Type: GrantFiled: March 25, 1997Date of Patent: June 27, 2000Assignee: Texas Instruments IncorporatedInventor: Lee D. Whetsel, Jr.
-
Patent number: 5687179Abstract: A serial scan path communication architecture includes a plurality of circuits (30), some of which may include a memory (36). A memory access controller (38) is included on circuits with a memory (36) such that serial data may be written to and written from the memories without having to repetitively cycle through multiple shift operations.Type: GrantFiled: March 29, 1995Date of Patent: November 11, 1997Assignee: Texas Instruments IncorporatedInventors: Lee D. Whetsel, Jr., Benjamin H. Ashmore, Jr.
-
Patent number: 5631911Abstract: A test cell (12) provides boundary scan testing in an integrated circuit (10). The test cell (12) comprises two memories, a flip-flop (24) and a latch (26), for storing test data. A first multiplexer (22) selectively connects one of a plurality of inputs to the flip-flop (24). The input of the latch (26) is connected to output of the flip-flop (24). The output of the latch (26) is connected to one input of a multiplexer (28), the second input to the multiplexer (28) being a data input (DIN) signal. A control bus (17) is provided for controlling the multiplexers (22, 28), flip-flop (24) and latch (26). The test cell allows input data to be observed and output data to be controlled simultaneously.Type: GrantFiled: June 7, 1995Date of Patent: May 20, 1997Assignee: Texas Instruments IncorporatedInventor: Lee D. Whetsel, Jr.
-
Patent number: 5623500Abstract: An event qualification architecture comprises event qualification cells (24) having an internal memory for detecting qualification events. The event qualification cells (24) output a signal indicating when a match has occurred, which is interpreted by an event qualification module (22). The event qualification module controls the test circuitry which may include test cell registers (14, 16) and test memory (28). A number of protocols are provided which can be designed into a circuit to provide the timing and control required to activate test logic in the circuit during normal system operation.Type: GrantFiled: October 13, 1995Date of Patent: April 22, 1997Assignee: Texas Instruments IncorporatedInventor: Lee D. Whetsel, Jr.
-
Patent number: 5602855Abstract: A test cell (12) provides boundary scan testing in an integrated circuit (10). The test cell (12) comprises two memories, a flip-flop (24) and a latch (26), for storing test data. A first multiplexer (22) selectively connects one of a plurality of inputs to the flip-flop (24). The input of the latch (26) is connected to output of the flip-flop (24). The output of the latch (26) is connected to one input of a multiplexer (28), the second input to the multiplexer (28) being a data input (DIN) signal. A control bus (17) is provided for controlling the multiplexers (22, 28), flip-flop (24) and latch (26). The test cell allows input data to be observed and output data to be controlled simultaneously.Type: GrantFiled: October 12, 1995Date of Patent: February 11, 1997Assignee: Texas Instruments IncorporatedInventor: Lee D. Whetsel, Jr.
-
Patent number: 5495487Abstract: A test cell (12) provides boundary scan testing in an integrated circuit (10). The test cell (12) comprises two memories, a flip-flop (24) and a latch (26), for storing test data. A first multiplexer (22) selectively connects one of a plurality of inputs to the flip-flop (24). The input of the latch (26) is connected to output of the flip-flop (24). The output of the latch (26) is connected to one input of a multiplexer (28), the second input to the multiplexer (28) being a data input (DIN) signal. A control bus (17) is provided for controlling the multiplexers (22, 28), flip-flop (24) and latch (26). The test cell allows input data to be observed and output data to be controlled simultaneously.Type: GrantFiled: February 14, 1994Date of Patent: February 27, 1996Assignee: Texas Instruments IncorporatedInventor: Lee D. Whetsel, Jr.
-
Patent number: 5353308Abstract: An event qualification architecture comprises event qualification cells (24) having an internal memory for detecting qualification events. The event qualification cells (24) output a signal indicating when a match has occurred, which is interpreted by an event qualification module (22). The event qualification module controls the test circuitry which may include test cell registers (14, 16) and test memory (28). A number of protocols are provided which can be designed into a circuit to provide the timing and control required to activate test logic in the circuit during normal system operation.Type: GrantFiled: October 8, 1993Date of Patent: October 4, 1994Assignee: Texas Instruments IncorporatedInventor: Lee D. Whetsel, Jr.
-
Patent number: 5084874Abstract: A test cell (12) provides boundary scan testing in an integrated circuit (10). The test cell (12) comprises two memories, a flip-flop (24) and a latch (26), for storing test data. A first multiplexer (22) selectively connects one of a plurality of inputs to the flip-flop (24). The input of the latch (26) is connected to output of the flip-flop (24). The output of the latch (26) is connected to one input of a multiplexer (28), the second input to the multiplexer (28) being a data input (DIN) signal. A control bus (17) is provided for controlling the multiplexers (22, 28), flip-flop (24) and latch (26). The test cell allows input data to be observed and output data to be controlled simultaneously.Type: GrantFiled: June 25, 1990Date of Patent: January 28, 1992Assignee: Texas Instruments IncorporatedInventor: Lee D. Whetsel, Jr.
-
Patent number: 4872169Abstract: A method of testing circuitry is by the application of scan design which consists of a series of shift registers or latches which form a serial scan path through a logic circuit. The scan path can be used to observe and control logic elements in the design via serial scan operations. The present invention allows a continuous scan path to be compressed or expanded so that the scan path only passes through the desired logic element(s) to be tested. Devices connected on the serial scan path (or ring) can be selected or deselected thus allowing the serial path to either flow through or bypass a given logic circuit's internal scan path. The invention can be used to create a hierarchical scan network consisting of a primary scan ring from which a multiplicity of scan sub-rings may be accessed.Type: GrantFiled: December 8, 1988Date of Patent: October 3, 1989Assignee: Texas Instruments IncorporatedInventor: Lee D. Whetsel, Jr.
-
Patent number: 4857835Abstract: Test logic may be included in the design of an integrated circuit (IC) to facilitate testability. In most instances, an IC's test logic can only be activated while the IC, or logic sections within the IC, are placed in a non-functional test mode. The present invention is directed toward an event qualification structure providing the timing and control required to activate an IC's test logic during normal functional operation.Type: GrantFiled: November 5, 1987Date of Patent: August 15, 1989Assignee: Texas Instruments IncorporatedInventor: Lee D. Whetsel, Jr.