Patents by Inventor Lee Dobson McFearin

Lee Dobson McFearin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200050376
    Abstract: It is possible to reduce the latency attributable to memory protection in shared memory systems by performing access protection at a central Data Ownership Manager (DOM), rather than at distributed memory management units in the central processing unit (CPU) elements (CEs) responsible for parallel thread processing. In particular, the DOM may monitor read requests communicated over a data plane between the CEs and a memory controller, and perform access protection verification in parallel with the memory controller's generation of the data response. The DOM may be separate and distinct from both the CEs and the memory controller, and therefore may generally be able to make the access determination without interfering with data plane processing/generation of the read requests and data responses exchanged between the memory controller and the CEs.
    Type: Application
    Filed: October 21, 2019
    Publication date: February 13, 2020
    Inventors: Sushma Wokhlu, Lee Dobson McFearin, Alan Gatherer, Hao Luan
  • Patent number: 10452287
    Abstract: It is possible to reduce the latency attributable to memory protection in shared memory systems by performing access protection at a central Data Ownership Manager (DOM), rather than at distributed memory management units in the central processing unit (CPU) elements (CEs) responsible for parallel thread processing. In particular, the DOM may monitor read requests communicated over a data plane between the CEs and a memory controller, and perform access protection verification in parallel with the memory controller's generation of the data response. The DOM may be separate and distinct from both the CEs and the memory controller, and therefore may generally be able to make the access determination without interfering with data plane processing/generation of the read requests and data responses exchanged between the memory controller and the CEs.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: October 22, 2019
    Assignee: FUTUREWEI TECHNOLOGIES, INC.
    Inventors: Sushma Wokhlu, Lee Dobson Mcfearin, Alan Gatherer, Hao Luan
  • Patent number: 10387355
    Abstract: Disclosed is method for operating an interposer that includes assigning a binary port weight to a plurality of input ports of the interposer. The sum of all of the port weights is less than or equal to a number of traversals available to the interposer in a cycle. A traversal counter is set zero at the beginning of each cycle. The output of the traversal counter is a binary number of m bits. A mask is generated when a bit of the traversal counter transitions from a zero to a one. The mask is generated having the m?k+1 bit of the mask equal to one and all other bits of the mask equal to zero. Data is transmitted from each port when both the binary port weight and the mask have a one in the same bit position.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: August 20, 2019
    Assignee: FUTUREWEI TECHNOLOGIES, INC.
    Inventors: Peter Yan, Alex Elisa Chandra, Lee Dobson McFearin, Fang Yu, Alan Gatherer
  • Patent number: 10185606
    Abstract: Methods and apparatus for inter-process communication are provided. A circuit may have a plurality of clusters, and at least one cluster may have a computation element (CE), a memory operatively coupled with the CE, and an autonomic transport system (ATS) block operatively coupled with the CE and the memory. The ATS block may be configured to perform inter-process communication (IPC) for the at least one cluster. In one embodiment, the ATS block may transfer a message to a different cluster based on a request from the CE. In another embodiment, the ATS block may receive a message by allocating a buffer in the memory and write the message into the buffer. The ATS block may also be configured to manage synchronization and schedule tasks for the CE.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: January 22, 2019
    Assignee: Futurewei Technologies, Inc.
    Inventors: Peter Yan, Alan Gatherer, Alex Elisa Chandra, Lee Dobson Mcfearin, Mark Brown, Debashis Bhattacharya, Fang Yu, Xingfeng Chen, Yan Bei, Ke Ning, Chushun Huang, Tong Sun, Xiaotao Chen
  • Publication number: 20180321939
    Abstract: Technology for providing data to a processing unit is disclosed. A computer processor may be divided into a master processing unit and consumer processing units. The master processing unit at least partially decodes a machine instruction and determines whether data is needed to execute the machine instruction. The master processing unit sends a request to memory for the data. The request may indicate that the data is to be sent from the memory to a consumer processing unit. The data sent by the memory in response to the request may be stored in local read storage that is close to the consumer processing unit for fast access. The master processing unit may also provide the machine instruction to the consumer processing unit. The consumer processing unit may access the data from the local read storage and execute the machine instruction based on the accessed data.
    Type: Application
    Filed: May 4, 2017
    Publication date: November 8, 2018
    Applicant: Futurewei Technologies, Inc.
    Inventors: Alan Gatherer, Sushma Wokhlu, Peter Yan, Ywhpyng Harn, Ashish Rai Shrivastava, Tong Sun, Lee Dobson McFearin
  • Publication number: 20170371570
    Abstract: It is possible to reduce the latency attributable to memory protection in shared memory systems by performing access protection at a central Data Ownership Manager (DOM), rather than at distributed memory management units in the central processing unit (CPU) elements (CEs) responsible for parallel thread processing. In particular, the DOM may monitor read requests communicated over a data plane between the CEs and a memory controller, and perform access protection verification in parallel with the memory controller's generation of the data response. The DOM may be separate and distinct from both the CEs and the memory controller, and therefore may generally be able to make the access determination without interfering with data plane processing/generation of the read requests and data responses exchanged between the memory controller and the CEs.
    Type: Application
    Filed: June 24, 2016
    Publication date: December 28, 2017
    Inventors: Sushma Wokhlu, Lee Dobson Mcfearin, Alan Gatherer, Hao Luan
  • Publication number: 20170293586
    Abstract: Disclosed is method for operating an interposer that includes assigning a binary port weight to a plurality of input ports of the interposer. The sum of all of the port weights is less than or equal to a number of traversals available to the interposer in a cycle. A traversal counter is set zero at the beginning of each cycle. The output of the traversal counter is a binary number of m bits. A mask is generated when a bit of the traversal counter transitions from a zero to a one. The mask is generated having the m?k+1 bit of the mask equal to one and all other bits of the mask equal to zero. Data is transmitted from each port when both the binary port weight and the mask have a one in the same bit position.
    Type: Application
    Filed: April 12, 2016
    Publication date: October 12, 2017
    Inventors: Peter Yan, Alex Elisa Chandra, Lee Dobson McFearin, Fang Yu, Alan Gatherer
  • Publication number: 20170293512
    Abstract: Methods and apparatus for inter-process communication are provided. A circuit may have a plurality of clusters, and at least one cluster may have a computation element (CE), a memory operatively coupled with the CE, and an autonomic transport system (ATS) block operatively coupled with the CE and the memory. The ATS block may be configured to perform inter-process communication (IPC) for the at least one cluster. In one embodiment, the ATS block may transfer a message to a different cluster based on a request from the CE. In another embodiment, the ATS block may receive a message by allocating a buffer in the memory and write the message into the buffer. The ATS block may also be configured to manage synchronization and schedule tasks for the CE.
    Type: Application
    Filed: April 12, 2016
    Publication date: October 12, 2017
    Inventors: Peter Yan, Alan Gatherer, Alex Elisa Chandra, Lee Dobson Mcfearin, Mark Brown, Debashis Bhattacharya, Fang Yu, Xingfeng Chen, Yan Bei, Ke Ning, Chushun Huang, Tong Sun, Xiaotao Chen
  • Publication number: 20170168792
    Abstract: A method includes obtaining, by a first processor, a first software architecture description file and obtaining, by the first processor, a platform independent model file. The method also includes obtaining, by the first processor, a platform architecture definition file and performing, by the first processor, a first source-to-source compilation in accordance with the first software architecture description file, the platform independent model file, and the platform architecture definition file, to produce generated interface code. Additionally, the method includes generating, by the first processor, run time code, in accordance with the generated interface code and running, by a second processor in real time, the run time code.
    Type: Application
    Filed: December 14, 2016
    Publication date: June 15, 2017
    Inventors: Debashis Bhattacharya, Alan Gatherer, Mark Brown, Lee Dobson McFearin, Alex Elisa Chandra, Ashish Rai Shrivastava
  • Publication number: 20170139740
    Abstract: An embodiment method includes receiving, by an intellectual property (IP) block within a computing system, a transaction request and determining, by the IP block, a context corresponding to the transaction request. The method further includes determining, by the IP block, a view of the computing system defined by the context and processing, by the IP block, the transaction request in accordance with the view of the computing system defined by the context.
    Type: Application
    Filed: November 12, 2015
    Publication date: May 18, 2017
    Applicant: FUTUREWEI TECHNOLOGIES, INC.
    Inventors: Lee Dobson McFearin, Alan Gatherer, Yan Bei