Abstract: An apparatus has processing circuitry, an instruction decoder, and capability registers, each capability register to store a capability comprising a pointer and constraint metadata for constraining valid use of the pointer/capability. In response to a capability-generating address calculating instruction specifying an offset value, a reference capability register is selected as one of a program counter capability register and a further capability register. A result capability is generated for which the pointer of the result capability indicates a window address identifying a selected window within an address space, the selected window being offset from a reference window by a number of windows determined based on the offset value of the capability-generating address calculating instruction. The reference window comprises the window comprising an address indicated by the pointer of the reference capability register.

Abstract: An apparatus and method are provided for storing bounded pointers. One example apparatus comprises a storage comprising storage elements to store bounded pointers, each bounded pointer comprising a pointer value and associated attributes including at least range information, and processing circuitry to store a bounded pointer in a chosen storage element. The storing process comprises storing in the chosen storage element a pointer value of the bounded pointer, and storing in the storage element the range information of the bounded pointer, such that the range information indicates both a read range of the bounded pointer and a write range of the bounded pointer that differs to the read range. The read range comprises at least one memory address for which reading is allowed when using the bounded pointer, and the write range comprises at least one memory address to which writing is allowed when using the bounded pointer.

Abstract: An apparatus and method are provided for storing bounded pointers. One example apparatus comprises a storage comprising storage elements to store bounded pointers, each bounded pointer comprising a pointer value and associated attributes including at least range information, and processing circuitry to store a bounded pointer in a chosen storage element. The storing process comprises storing in the chosen storage element a pointer value of the bounded pointer, and storing in the storage element the range information of the bounded pointer, such that the range information indicates both a read range of the bounded pointer and a write range of the bounded pointer that differs to the read range. The read range comprises at least one memory address for which reading is allowed when using the bounded pointer, and the write range comprises at least one memory address to which writing is allowed when using the bounded pointer.

Abstract: A processing apparatus includes floating point arithmetic circuitry coupled to monitoring circuitry. The monitoring circuitry stores exponent limit data indicating at least one of a maximum exponent value and a minimum exponent value processed when performing the floating point arithmetic operations. The monitoring circuitry may be selectively enabled in dependence upon a virtual machine identifier, an application specific identifier or a program counter value range. Exponent limit data may be gathered in respect of different portions of the floating point arithmetic circuitry and/or may be aggregated to form global exponent limit data for the system.

Abstract: A data processing apparatus is disclosed that comprises monitoring circuitry for monitoring accesses to a plurality of addressable locations within said data processing apparatus that occur between start and end events said monitoring circuitry comprising: an address location store for storing data identifying said plurality of addressable locations to be monitored and a monitoring data store; said monitoring circuitry being responsive to detection of said start event to detect accesses to said plurality of addressable locations and to store monitoring data relating to a summary of said detected accesses in said monitoring data store; and said monitoring circuitry being responsive to detection of said end event to stop collecting said monitoring data; said monitoring circuit being responsive to detection of a flush event to output said stored monitoring data and to flush said monitoring data store.

Abstract: A data processing system is provided with processing circuitry as well as a bank of 64-bit registers. An instruction decoder decodes arithmetic instructions and logical instruction specifying arithmetic operations and logical operations to be performed upon operands stored within the 64-bit registers. The instruction decoder is responsive to an operand size field SF within the arithmetic instructions and the logical instructions specifying whether the operands are 64-bit operands or 32-bit operands where all of the operands are 64-bit operands or all of the operands are 32-bit operands. If a switch is made to a lower exception level, then a check is made as to whether or not a register being used was previously subject to a 64-bit write to that register. If such a 64-bit write had previously taken place, then the upper 32-bits are flushed so as to avoid data leakage from the higher exception level.

Abstract: A processing apparatus 200 includes floating point arithmetic circuitry 214, 216 coupled to monitoring circuitry 226. The monitoring circuitry stores exponent limit data indicating at least one of a maximum exponent value and a minimum exponent value processed when performing the floating point arithmetic operations. The monitoring circuitry may be selectively enabled in dependence upon a virtual machine identifier, an application specific identifier or a program counter value range. Exponent limit data may be gathered in respect of different portions of the floating point arithmetic circuitry and/or may be aggregated to form global exponent limit data for the system.

Abstract: A data processing system 2 is provided with processing circuitry 8, 10, 12 as well as a bank of 64-bit registers 6. An instruction decoder 14 decodes arithmetic instructions and logical instruction specifying arithmetic operations and logical operations to be performed upon operands stored within the 64-bit registers 6. The instruction decoder 14 is responsive to an operand size field SF within the arithmetic instructions and the logical instructions specifying whether the operands are 64-bit operands or 32-bit operands. Each 64-bit register stores either a single 64-bit operand or a single 32-bit operand. For a given arithmetic instruction and logical instruction either all of the operands are 64-bit operands or all of the operands are 32-bit operands. A plurality of exception levels arranged in a hierarchy of exception levels may be supported.

Abstract: Memory address space is divided into domains and instruction access control circuitry is used to detect when the memory address from which an instruction to be executed is fetched has crossed a domain boundary and changed and in such cases to conduct a check to ensure that the instruction within the new domain is a permitted instruction of a permitted form. The permitted instruction can be arranged to be a no operation instruction other than in respect of the instruction access control circuitry, in order to assist backward compatibility.

Abstract: A data processing apparatus is disclosed that comprises monitoring circuitry for monitoring accesses to a plurality of addressable locations within said data processing apparatus that occur between start and end events said monitoring circuitry comprising: an address location store for storing data identifying said plurality of addressable locations to be monitored and a monitoring data store; said monitoring circuitry being responsive to detection of said start event to detect accesses to said plurality of addressable locations and to store monitoring data relating to a summary of said detected accesses in said monitoring data store; and said monitoring circuitry being responsive to detection of said end event to stop collecting said monitoring data; said monitoring circuit being responsive to detection of a flush event to output said stored monitoring data and to flush said monitoring data store.

Abstract: Memory address space is divided into domains and instruction access control circuitry is used to detect when the memory address from which an instruction to be executed is fetched has crossed a domain boundary and changed and in such cases to conduct a check to ensure that the instruction within the new domain is a permitted instruction of a permitted form. The permitted instruction can be arranged to be a no operation instruction other than in respect of the instruction access control circuitry, in order to assist backward compatibility.